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Slice assignment problem - help requested

 
 
Daku
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Posts: n/a
 
      11-18-2009
Could some VHDL guru please help me ? My source file is as follows and
I am using the Alliance 5.0 toolset.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;


ENTITY ram IS
port ( A : in std_logic_vector(5 downto 0);
CEB : in std_logic;
WEB : in std_logic;
REB : in std_logic;
INN : in std_logic_vector(23 downto 0);
OUTT : out std_logic_vector(23 downto 0)
);
END ram;

ARCHITECTURE dataflow_view OF ram IS
SUBTYPE INDX IS std_logic_vector(0 to 31);
SIGNAL index : INDX;

SUBTYPE TYPE_WORD IS std_logic_vector(23 downto 0);
TYPE TYPE_RAM IS ARRAY(31 DOWNTO 0) OF TYPE_WORD;
SIGNAL memory : TYPE_RAM := ((OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),

(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),

(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'));
SUBTYPE J IS INTEGER RANGE 1 TO 32;
SIGNAL II : J;

BEGIN

RAM_0 : PROCESS( WEB )
VARIABLE cnt : INTEGER;

BEGIN
IF (WEB='1' AND WEB'EVENT )
THEN IF (REB='0') THEN
FOR I IN 1 TO 32 LOOP
II <= I;
EXIT WHEN index(II) = '0';
END LOOP;
--memory( CONV_INTEGER( A ) ) <= INN;
END IF;
END IF;
END PROCESS RAM_0;

RAM_1 : PROCESS( REB )

BEGIN
IF (REB='1' AND REB'EVENT)
THEN IF (CEB='1')
THEN OUTT <= memory( CONV_INTEGER(A) );
END IF;
END IF;
END PROCESS RAM_1;

END dataflow_view;

I am getting a compile time error as:
--> Run VHDL Compiler
--> Compile file ram
vasy_array.613 Illegale use of slice assignation

I am sure the bug is in the for loop, but not sure how to get around
it. Any hints, suggestions would be of immense help. Thanks in advance
for your help.

 
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