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Alliance 5.0 stimulus file syntax error - Request help

 
 
Daku
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      11-13-2009
Could some VHDL guru please help me ? I have used VHDL in the past,
but am a newbie to the Alliance toolset, I am using version 5.0. I
have a very simple RAM architecture file as:
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;


ENTITY ram IS
port ( A : in std_logic_vector(5 downto 0);
CEB, WEB : in std_logic;
INN : in std_logic_vector(7 downto 0);
OUTT : out std_logic_vector(7 downto 0)
);
END ram;

ARCHITECTURE dataflow_view OF ram IS
SUBTYPE TYPE_WORD IS
std_logic_vector(7 downto 0);
TYPE TYPE_RAM IS
ARRAY(63 DOWNTO 0) OF TYPE_WORD;
SIGNAL memory : TYPE_RAM;

BEGIN
OUTT <= memory( CONV_INTEGER( A ) );
RAM_0 : PROCESS( CEB )
BEGIN
IF (CEB='1' AND CEB'EVENT )
THEN IF (WEB='0')
THEN
memory( CONV_INTEGER( A ) ) <= INN;
END IF;
END IF;
END PROCESS RAM_0;
END dataflow_view;

The stimulus file is as:

in a(5 downto 0) X;;;;;
in ceb B;;
in web B;;
in inn(7 downto 0) X;;;;;;;
out outt(7 downto 0) X;;;;;;

begin

< 0ns>: 1 1 0 2 ?*;
< +10ns>: 2 1 0 3 ?*;
< +10ns>: 3 1 0 4 ?*;
< +10ns>: 4 1 0 5 ?*;
< +10ns>: 5 1 0 6 ?*;

end;

I am getting the following errors:
searching `ram` ...
BEH : Compiling `ram.vbe` (Behaviour) ...
making GEX ...

searching pattern file : `ram` ...
PAT : Error 10 line 10 : illegal value for `web` format `B`PAT : Error
5 line 10 : cannot compare the value of input `inn 7`PAT : Error 15
line 10 : no enough input-output values
PAT : Error 10 line 11 : illegal value for `web` format `B`PAT : Error
5 line 11 : cannot compare the value of input `inn 7`PAT : Error 15
line 11 : no enough input-output values
PAT : Error 10 line 12 : illegal value for `web` format `B`PAT : Error
5 line 12 : cannot compare the value of input `inn 7`PAT : Error 15
line 12 : no enough input-output values
PAT : Error 10 line 13 : illegal value for `web` format `B`PAT : Error
5 line 13 : cannot compare the value of input `inn 7`PAT : Error 15
line 13 : no enough input-output values
PAT : Error 10 line 14 : illegal value for `web` format `B`PAT : Error
5 line 14 : cannot compare the value of input `inn 7`PAT : Error 15
line 14 : no enough input-output values

Could someone please provide some pointers as to what might be my
mistake ? Any hints, suggestions would be of immense help. Thanks in
advance for your help.
 
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Mike Treseler
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Posts: n/a
 
      11-13-2009
Daku wrote:
> I have used VHDL in the past,
> but am a newbie to the Alliance toolset, I am using version 5.0. I
> have a very simple RAM architecture file as:


Does the target device have block ram?
Does your ram template synthesize to the expected block ram?
Does alliance have some version of modelsim?

-- Mike Treseler
 
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