Generic Comparator using VHDL

Hi all,

I ve designed a generic VHDL comparator in two ways. Total number of Inputs are N, which is always be 2^n (n=2,3,4..).

1.Comparing the first and second input and the result is compared with the third input,this result is compared with the four input and so on. So for 8 inputs, 7 levels of comparison was used.

This method increased the delay of my design, so I redesigned the code as explained below.

2. At the first level, compare the inputs1 and 2, 3 and 4, 5 and 6. At the next level, result of 1&2, 3&4 are compared and so on. This decreased the number of logic levels to 3 and gives me better performance.

One Problem with the second method is, I ve declared two dimensional array of size (N,Logic levels) to store the result of each comparision.First level outputs are stored at location (0 to N,1). Note at next levels outputs are stored are locations (0 to N/2,2).Similary next level outputs are stored at locations (0 to N/4,3).

See at each level, my number of results stored are reducing, But VHDL doesn't allow an array to be created like this. So I declared an array of size N for all logic levels. This gives me warning for the unaltered array location ,ex, (N/2 to N) at logic level 2. I want warning-free synthesis. Can you help me?

Note: If the questions seems to be weird, please let know. I can elobrate more!!

sridar

[joris]

You might use recursion for this; that way, you can define the one dimensional array needed for that invocation - either a recursive function, or recursion on entity level - both should work equally well;

If everything is right, that should render what you want

joris