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[Alterah]

Hello, I am trying to learn how to utilize VHDL to implement various configurations of logic gates, etc. However, I am having a difficult time. Any help is appreciated. The problem is this:

1. Implement a 4 input AND gate using 3 2 input AND gates.

Basically what I have is A,B,C,D,F,G,H.

A and B go through an AND gate. Output is F.
C and D go through an AND gate. Output is G.

Then F and G go through an AND gate. Output is H.

Here's my code...which does not compile.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY myAND1 IS
PORT (
A,B,C,D: IN STD_LOGIC;
F,G,H : OUT STD_LOGIC);
END myAND1;

ARCHITECTURE AND1 of myAND1 IS
BEGIN
F <= A AND B;
END ARCHITECTURE AND1;

ARCHITECTURE AND2 of myAND1 IS
BEGIN
G <= C AND D;
END ARCHITECTURE AND2;

ARCHITECTURE AND3 of myAND1 IS
BEGIN
H <= F AND G;
END ARCHITECTURE AND3;

EDIT: I believe I have fixed it. Guess I was a little too hasty in posting.

[debayan_p]

Take the VHDL book by Douglas Perry and solve the exercises given at the end of each chapter. That will solve ur problem !