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VHDL - GTKWave not showing signals of user types

 
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Old 11-04-2009, 04:19 PM   #1
Default GTKWave not showing signals of user types


Hello,

I am writing some VHDL code and try to simulate it with GTKWave. The problem is that I can not see the signals that are defined as user types. All the other signals appear in the simulator.

signal rout_amba, ri_amba : amba_registers; -- not visible
signal rout_cb, ri_cb : cb_registers; -- not visible

signal internal_rst : std_logic := '0'; -- visible
signal output : std_logic_vector(31 downto 0); -- visible

Does anybody has any idea why?

Thanks,
Mihai


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