Creating delay in divider

Hello,

I have a design in which I have a 1/x operation, which cannot be
optimized away. I'm using the fixed-point library of the new vhdl
standard, which supplies me with a reciprocal function.

Synthesizing such a design in synplify is giving me an sdiv block, and
a very large delay (probably due to the fact that it operates in one
clock cycle).

How can I modify my design such that I can still use the reciprocal
function of the fixed point library, but have a delay of multiple
clock cycles? Or do I have to build a dedicated divider?

Greetings,
Tim

THurkmans

On Nov 4, 10:22*am, THurkmans <timhurkm...@gmail.com> wrote:

> How can I modify my design such that I can still use the reciprocal
> function of the fixed point library, but have a delay of multiple
> clock cycles? Or do I have to build a dedicated divider?
>

Google for lpm_divide. It's a divider that operates on multiple clock
cycles.

KJ

KJ