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VHDL - Generate Statement

 
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Old 11-02-2009, 05:40 AM   #1
Default Generate Statement


Hi all, I want to know whether the following approach is correct using for generate statement

l1: For i in 0 to 5 generate

l2: For j in 0 to (2**(5-i))-1 generate

Note that in the loop 2, I am referring loop1's value i.


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Old 11-03-2009, 08:13 AM   #2
joris
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yes that should work fine


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