Selecting generic at simulation time.

I have a testbench which reads data from a memory, which is
initialised with data from a file, the file name is a generic in the
memory model.

Is there some way to start the simulation which then asks which file
I'd like to use to initialise the memory before the sim progresses?
TIA, Niv.

Niv (KP)

You can also use environment variables when opening a file.
I've succeded both with aldecs and mentors vhdl simulators,
use $$MY_ENV_VAR for riviera, use $MY_ENV_VAR for modelsim.

So something similar to this should work (can' test my self right now)
file_open(status, "$$MY_PATH/my_file.ext", L.all, READ_MODE);

HTH -- Pontus

Pontus

If the file is opened/read dynamically in a process, then you cannot
initialize the memory array via its declaration. With a generic, you
can initialize the array declaration with a function call that uses
the generic, opens the file, reads the data and returns an initialized
array. This initialization is done during the VHDL elaboration phase,
which is "hidden" at the beginning of many simulators (before the
actual simulation starts), but is an explicit step on others (e.g.
Cadence).

Andy

Andy