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Selecting generic at simulation time.

 
 
Niv (KP)
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      10-31-2009
I have a testbench which reads data from a memory, which is
initialised with data from a file, the file name is a generic in the
memory model.

Is there some way to start the simulation which then asks which file
I'd like to use to initialise the memory before the sim progresses?
TIA, Niv.
 
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Pontus
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      10-31-2009
You can also use environment variables when opening a file.
I've succeded both with aldecs and mentors vhdl simulators,
use $$MY_ENV_VAR for riviera, use $MY_ENV_VAR for modelsim.

So something similar to this should work (can' test my self right now)
file_open(status, "$$MY_PATH/my_file.ext", L.all, READ_MODE);

HTH -- Pontus
 
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Andy
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      11-02-2009
If the file is opened/read dynamically in a process, then you cannot
initialize the memory array via its declaration. With a generic, you
can initialize the array declaration with a function call that uses
the generic, opens the file, reads the data and returns an initialized
array. This initialization is done during the VHDL elaboration phase,
which is "hidden" at the beginning of many simulators (before the
actual simulation starts), but is an explicit step on others (e.g.
Cadence).

Andy
 
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logic_guy
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      12-30-2009
I've also written testbenches that pause and wait for the user to source
a tcl script. The tcl script sets a VHDL variable (using the "change"
command in Modelsim), issues a "force" command on a signal to trigger an
event, and that starts a process that does some massaging of the
variable (mainly to determine to number of non-blank characters) and
feeds that to a VHDL open statement to open the requested file.

Charles Bailey


 
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