vhdl range in verilog

Hi,

how do I use a vhdl range type into a verilog vector?

eg.
vhdl:

type InputRange is
(
line01,
line02,
line03,
....
);

and then in verilog I want to use it like this:

wire [32:0] In_s;
assign In_s[line03] = other_signal;

Is it possible?

thanks
ivan

Ivan

Ivan wrote:

> how do I use a vhdl range type into a verilog vector?
> eg.
> vhdl:
> type InputRange is
> (
> line01,
> line02,
> line03,
> ...
> );


Last I used verilog,
enumerations were a do-it-yourself project
something like:

parameter line01 = 1,
line02 = 2,
line03 = 3;

Good luck.

-- Mike Treseler

Mike Treseler