Representing the buffer with logic gates,flipflops

Hello all,
Does anyone tried implementing the an array with logic gates, flipflops in vhdl??
I f so, can u pls give me idea ...
** No need of source code...idea to start..

KSR

[jeppe]

Try this page - could give you inspiration:

jjmk.dk/MMMI/Exercises/05_Counters_Shreg/No4_LIFO_Stack/index.htm

jeppe

[KSR]

@jeppe,
i tried to define an array ..As u can see instead of using constant sample i tried to write code such that for every rising edge of clk the array should get filled..

package arrays is
type a1 is array (1 to 7) of integer range 0 to 8;

--constant sample:a1:=(1,2,3,4,5,6,7); to define an array activate this..
end arrays;

Library ieee;
Library work;
use ieee.std_logic_1164.all;
use work.arrays.all;

entity rbf2410 is
port(i : in integer range 0 to 8;
clk : in std_logic;
output : out integer range 0 to ;
end rbf2410;

architecture rbf1 of rbf2410 is
signal arr : a1;
begin
process(clk)
variable i : integer range 0 to 8;
begin
if rising_edge(clk) then
i:=i+1;
if (i<7) then
arr(i)<=i;
output<=arr(i);
-- i<=i+1;
else
arr(i)<=i;
output<=arr(i);
i:=0;
end if;
end if;
end process;
end rbf1;


But i am not getting exact o/p in waveform..like there is a delay in o/p
Can u hav a look at this??

KSR

[jeppe]

Library ieee;
Library work;
use ieee.std_logic_1164.all;
use work.arrays.all;

entity rbf2410 is
      port(i : in integer range 0 to 8;
      clk : in std_logic;
      output : out integer range 0 to ;
end rbf2410;

architecture rbf1 of rbf2410 is
    -- signal arr : a1;
begin
    process(clk)
         variable i : integer range 0 to 8;
         variable arr : a1;
    begin
        if rising_edge(clk) then
             i:=i+1;
             if (i<7) then
                  arr(i):=i;
                  output<=arr(i);
                  -- i<=i+1;
             else
                  arr(i):=i;
                  output<=arr(i);
                  i:=0;
            end if;
        end if;
     end process;
end rbf1;

this should remove your delay - search the net for the interactive book - EVITA VHDL - chapter 6 will answer you question

Jeppe

jeppe

[KSR]

@jeppe,

delay got removed in o/p...and i read e-vita..Thanks for sharing it!!
heres a quick question..
i am observed that my o/p is starting with 0 value followed by given input values..dis is because of falling edge of clk..is thr anyway to get rid of dis 0??

In addition i want to know,
1)Can we get the values stored in an array ...like wise print statement displaying the values of an array in C??(I am novice to this field donno this is a rite ques. or not)

2) Can we implement an array without a process statement???


Thanks,
KSR.

KSR

[jeppe]

Hi KSR

If your code for the purpose of simulation will some the operations be possible - like for instance some of the print like statemens.
Anyway will a simulator alllow ýou to display the content of an array.

Yes you can use an array without a process. But more "advanced" code will
take a process to implement.

jeppe

[KSR]

can u pls help me in figuring out ring buffer from that array code.
I tried but my empty, full signals are not incrementing even at clock edge..
Give me some idea how to start...

Waiting for reply..
Kavya.

KSR

[jeppe]

Whats the entity of your ringbuffer?

jeppe

[KSR]

entity rbf is

generic (
B : natural :=8; -- number of bit
W: natural :=4 -- number of address bit
);

port (

clk, reset : in std_logic;
rd, wr : in std_logic;
w_data : in std_logic_vector ( B-1 downto 0);
empty, full : out std_logic;
r_data : out std_logic_vector (B-1 downto 0)
);
end rbf;

heres the entity..
i got code compiled..but when i tried to view waveform by giving input data..output signals r blank(0)..

Thanks
KSR

KSR

[jeppe]

Hi Kavya

Try this code - I know you wanted hints - but you got some code instead which you can modify for your needs.

your welcome
Jeppe

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rbf is
      generic (
            B : natural :=8; -- number of bit
            W: natural :=4 -- number of address bit
            );
      port ( clk, reset : in std_logic;
             rd, wr : in std_logic;
             w_data : in std_logic_vector ( B-1 downto 0);
             empty, full : inout std_logic;
             r_data : out std_logic_vector (B-1 downto 0));
end rbf;

architecture Behavioral of rbf is
   type array_type is array (0 to 2**W-1) of std_logic_vector( B-1 downto 0);
   signal ringbuffer: array_type;
   signal w_index, r_index: std_logic_vector( W-1 downto 0);  --integer range 0 to 2**W-1;
   signal count:            std_logic_vector( W downto 0);
begin

   empty <= '1' when count=0    else '0';
   full  <= '1' when count=2**W else '0';
   r_data <= ringbuffer( conv_integer(r_index));
   
   process( clk)
      variable wr_edge, rd_edge: std_logic_vector( 1 downto 0) := "00";
   begin
      if rising_edge( clk) then
         if reset = '1' then
            w_index <= (others=>'0');
            r_index <= (others=>'0');
            count   <= (others=>'0');
            wr_edge := wr&wr;
            rd_edge := rd&rd;
         else
            if wr_edge="01" and full='0' then
               ringbuffer( conv_integer(w_index)) <= w_data;
               w_index <= w_index+1;
               count   <= count+1;
            end if;
            if rd_edge="01" and empty='0' then
               r_index <= r_index+1;
               count <= count-1;
            end if;
            wr_edge := wr_edge(0) & wr;
            rd_edge := rd_edge(0) & rd;
         end if;
      end if;
   end process;
   
end Behavioral;

jeppe