Representing the buffer with logic gates,flipflops

@jeppe,
Thanks for code.
i tried to compile it..i think i am not giving correct input values to i/p ports.
and one more doubt is that u have taken full,empty as inout ports...
in output waveform they are at Z value.
Is thr anyway to send my simulation waveform so that u can figure out whts going on worng??

Thanks,
KSR

KSR

[jeppe]

Hi KSR

I actually simulated and tested the design - TestBench below
the INOUT signals will not be Z unless you tell it to be so. The INOUT could be substituted with BUFFER if you like.

Your welcome
Jeppe

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY TB_rbf IS
END TB_rbf;
 
ARCHITECTURE behavior OF TB_rbf IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT rbf
    PORT( clk : IN  std_logic;
         reset : IN  std_logic;
         rd : IN  std_logic;
         wr : IN  std_logic;
         w_data : IN  std_logic_vector(7 downto 0);
         empty : INOUT  std_logic;
         full : INOUT  std_logic;
         r_data : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   signal rd : std_logic := '1';
   signal wr : std_logic := '1';
   signal w_data : std_logic_vector(7 downto 0) := (others => '0');

	--BiDirs
   signal empty : std_logic;
   signal full : std_logic;

 	--Outputs
   signal r_data : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
BEGIN
 
  --Instantiate the Unit Under Test (UUT)
   uut: rbf PORT MAP (
          clk => clk,
          reset => reset,
          rd => rd,
          wr => wr,
          w_data => w_data,
          empty => empty,
          full => full,
          r_data => r_data);

   -- Clock process definitions
   clk_process :process
   begin
      clk <= '0';
      wait for clk_period/2;
      clk <= '1';
      wait for clk_period/2;
   end process;

   -- Stimulus process
   stim_proc: process
   begin	
     reset <= '1';
     wait for clk_period*2;
     reset <= '0';       
     w_data <= "00010000";     
     wait for clk_period*2;
     
     for i in 0 to 17 loop
         w_data <= w_data+1;
         wr <= '0';
         wait for clk_period*2;
         wr <= '1';
         wait for clk_period*2;    
     end loop;

     for i in 0 to 17 loop
         rd <= '0';
         wait for clk_period*2;
         rd <= '1';
         wait for clk_period*2;    
     end loop;
      wait;
   end process;

END;

jeppe

[KSR]

@jeppe,
Okay i understood..Thanks..
Are there any nice books that i can refer for writing testbenches ...becuase i want to learn them..

KSR

[jeppe]

Most books do have chapters of about the topic testbenching.
But I can't give you a specific title.
The EVITA gives some hints about delays - My example above will be sufficent for most cases.

jeppe