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VHDL - Wait on statement

 
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Old 10-26-2009, 03:11 AM   #1
Default Wait on statement


Hi all,

i would need something like :

Wait on SIG1 OR Wait on SIG2 OR Wait on SIG3;

(my entity is asynch and i need to run the process every time a input sig change).

Thanks for your support,

David.

edit : wait on sig1,sig2,sig3 does that ?


darock

Last edited by darock : 10-26-2009 at 03:24 AM.
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Old 10-27-2009, 01:26 AM   #2
matchstick86
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as in the process will not proceed until a signal changes? are we talking about one or three signals?

personally I don't like using wait statements. I use a sensitivity list containing those signals so that whenever any of them changes, the process will kick in.

so you could try
Code:
process(sig1, sig2, sig3) is --variables or what have you begin ...

If that's not what you are looking for, perhaps:
Code:
WAIT ON (sig1 OR sig2 OR sig3);

Try them and let us know!


matchstick86
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Old 10-28-2009, 04:17 AM   #3
darock
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Thanks for the reply!

The second code is exactly the behavior i want .... but it doesn't seems to compile... (i use modelsim)

** Error: *******l.vhd(336): near "(": expecting "STRING" or "IDENTIFIER" or "<<"

i used the same syntax than you( just put my signal name)

(i can't use sensitivity list because i need "wait for" to emulate gate delay)

any idea?
Edit : ok i found

****://***.csee.umbc.edu/help/VHDL/sequential.html

wait on sig1, sig2; -- sensitivity clause, any event on any signal terminates wait

now i am sure ! thanks


darock

Last edited by darock : 10-28-2009 at 04:33 AM.
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