Idea to implement ring buffer

Hello all,
i am trying to implement a ring buffer of size 8.
The data given to fpga is sent to a ring buffer and it waits until buffer is full.Once it is full it should send data out so that avoiding data overwritten.
I would appreciate if anyone guide me through this vhdl code.

KSR

[KSR]

Hello everybody,
Pls help me how to design a ring buffer in vhdl..i am in dire need of it!!

KSR

[jeppe]

Hi - try this link (copy to the browser)

jjmk.dk/MMMI/Lessons/07_Memory/No6_FIFObuffers/index.htm

you will find a rather simple way to implement a ringbuffer, however will a solution which implement a counter to keep track of the numbers at the stack give some advantages.

jeppe

[KSR]

thanks,
i came to know that ring buffer is a fifo without enables..
whts this mean??

KSR

[KSR]

well, i tried this code for declaring an array
and i got the o/p as for every rising edge of clk a value is written into array
can anyone help me out how to develop ring buffer from it..

package arrays is
type a1 is array (1 to 7) of integer;
constant sample:a1:=(1,2,3,4,5,6,7);
end arrays;
Library ieee;
use ieee.std_logic_arith.all;
use work.arrays.all;
use ieee.std_logic_1164.all;

entity ringsam is
port(clk : in std_logic;
--inp : in INTEGER RANGE 0 to 3;
o : out integer
--a : inout a1
);
end ringsam;

architecture ringsam1 of ringsam is
begin
process (clk)
variable i : integer range 0 to 7;
begin
if rising_edge(clk)then
i:=i+1;
--for i in 0 to 7 loop
if (i<7) then
o<=sample(i);

else
o<=sample(i);
i:=0;
end if;
end if;

end process;
end ringsam1;

KSR