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Synthesis wrapper

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>I use simplify for synthesis,

I can also start SynplifyPro standa-lone:
When having one VHDL file "test_module.vhd" with one entity
"test_module" and two architectures "rtl" and "wrapped" ("wrapped"
declared after "rtl" and instantiating "test_module(rtl)" ),
SynplifyPro does synthesize the module with additional input and
output registers. But how can I tell SynplifyPro not to use the
architecture "wrapped" (that is to synthesize the original module with
architecture "rtl" only ) ?

When instantiating "test_module(wrapped)" in architecture "wrapped" I
get the error message: "Maximum design hierarchy component
instantiation depth exceeded: 251".


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If the wrapped architecture instantiates itself, without an if-
generate statement to eventually break the recursion, you have an
infinite recursion, but Symplify apparently only supports 251 levels
(not that any tool will support infinite recursion!)

Without further direction, compliant vhdl tools will assume the most
recently analyzed architecture is bound to the entity. In the case of
the single file, wrapped is compiled last, and it gets used by

If you want to use the rtl architecture in your design, simply
instantiate it by name in your design:

mod1: entity work.test_module(rtl)
port map ...

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Posts: n/a
On Oct 23, 4:59*pm, Mike Treseler <(E-Mail Removed)> wrote:
> Otherwise, quartus insists on a single top entity:
> "Note: The Quartus II software cannot process VHDL designs with two or
> more entities of the same name even if the entities are compiled into
> separate custom libraries."
> * * * -- Mike Treseler

I'm confused... how can ANY tool support more than one TOP level
entity (same name or not)?

VHDL itself does not allow two different entities of the same name,
compiled into the same library. The most recently analyzed entity will
overwrite any earlier ones. Entities are not overridden via different
signatures (port maps) like subprograms are. And how would an
architecture declare which of several same-named entities it is for?
Keep in mind that architectures must be compiled into the same library
as their entity(ies), so same-named entities in different libraries
does not cause a problem.

The limitation that Symplify cannot handle two different entities,
named the same, but compiled in different libraries is more
troubling. So if I use one piece of IP with another in a design,
compiled in separate libraries, I have to make sure they don't share
any common entity names? Ouch!


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Mike Treseler
Posts: n/a
Andy wrote:

> how can ANY tool support more than one TOP level
> entity (same name or not)?

Sorry, make that one entity max with the same id.
Same as Synplify.

-- Mike Treseler
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