Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > General Computer Discussion > Hardware > VHDL problem with variables

Reply
Thread Tools

VHDL problem with variables

 
 
krkrkr krkrkr is offline
Junior Member
Join Date: Jun 2009
Posts: 7
 
      10-16-2009
Hello,
I've a problem when calling a procedure a passing variable to it, I tried my code in Quartus and compiled without errors but when I tried xilinx XPS which I have to use, I got the following error (undefined signal "aprio")
The code is down, any help???

architecture rtl of mylogic is

signal x : integer range 0 to 15 := 0;
signal y : integer range 0 to 15 := 0;

procedure add_prio (variable aprio: in integer;
variable aout: inout integer) is
begin
aout := aout + aprio;
end procedure add_prio;

begin

add_proc: process(clk) is
variable prio : integer range 0 to 15 :=0;
variable out : integer range 0 to 15 :=0;

if clk'event and clk = '1' then
prio := x;
add_prio(prio, out);
y <= out;
end if;
end process add_proc;

end rtl;
 
Reply With Quote
 
 
 
 
vipinlal vipinlal is offline
Member
Join Date: Feb 2010
Posts: 39
 
      03-06-2010
you signals prio and out are declared as integers with range 0 to 15.
but in the declaration of your procedure
"add_prio (variable aprio: in integer; variable aout: inout integer) " you are giving integers with full or different range. i think this is the problem.Just change the range of the inputs and tell me whether it is working or not.


------------------------------
vhdlguru.blogspot.com --VHDL tuto site.
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Emacs VHDL-Mode Problem : vhdl-update-sensitivity-process omara007 VHDL 0 01-06-2010 03:47 AM
Put variables into member variables or function variables? tjumail@gmail.com C++ 9 03-23-2008 04:03 PM
VHDL-2002 vs VHDL-93 vs VHDL-87? afd VHDL 1 03-23-2007 09:33 AM
multiD-vhdl: Multi Dimensional Arrays (allowing generics on each dimension) for VHDL (including ports) albert.neu@gmail.com VHDL 2 03-21-2006 04:05 PM
what's the difference between VHDL 93 CONCATENATION and VHDL 87 CONCATENATION? walala VHDL 3 09-18-2003 04:17 AM



Advertisments