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VHDL problem with variables

krkrkr krkrkr is offline
Junior Member
Join Date: Jun 2009
Posts: 7
I've a problem when calling a procedure a passing variable to it, I tried my code in Quartus and compiled without errors but when I tried xilinx XPS which I have to use, I got the following error (undefined signal "aprio")
The code is down, any help???

architecture rtl of mylogic is

signal x : integer range 0 to 15 := 0;
signal y : integer range 0 to 15 := 0;

procedure add_prio (variable aprio: in integer;
variable aout: inout integer) is
aout := aout + aprio;
end procedure add_prio;


add_proc: process(clk) is
variable prio : integer range 0 to 15 :=0;
variable out : integer range 0 to 15 :=0;

if clk'event and clk = '1' then
prio := x;
add_prio(prio, out);
y <= out;
end if;
end process add_proc;

end rtl;
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vipinlal vipinlal is offline
Join Date: Feb 2010
Posts: 39
you signals prio and out are declared as integers with range 0 to 15.
but in the declaration of your procedure
"add_prio (variable aprio: in integer; variable aout: inout integer) " you are giving integers with full or different range. i think this is the problem.Just change the range of the inputs and tell me whether it is working or not.

------------------------------ --VHDL tuto site.
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