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Source code encryption

 
 
Paul Uiterlinden
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      10-06-2009
I'm in a situation where some IP written in VHDL must be sent to a customer
so he can simulate it. Of course we don't want to send the source code.

Normally, what we do is sending pre-compiled libraries, where the the VHDL
files are compiled using the -nodebug option of vcom. This is for
ModelSim/QuestaSim.

Now we're facing a customer who does not use ModelSim. Instead, he uses a
simulator by Cadence (Incisive, I suppose, or ncsim). We do not have
Cadence tools.

So, what's the best way to cope with this?

The first question is whether ncvhdl has a similar option as the -nodebug
option of vcom, hiding all internal signals and hierarchy. I have tried to
find the manual pages of ncvhdl on www.cadence.com but the search results
from that site are awful.

Second thought is using the new VHDL-2008 `PROTECT keyword. A data sheet on
the Incisive simulator however does not mention any 2008 support. Is this
correct?

As a last resort we could use some kind of obfuscator like Krypton by Leda
(if that still exists). But I'm not in favor of that idea.

Any answers/thoughts are welcome.
Thanks.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
 
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Petter Gustad
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      10-06-2009
Paul Uiterlinden <(E-Mail Removed)> writes:

> Normally, what we do is sending pre-compiled libraries, where the the VHDL
> files are compiled using the -nodebug option of vcom. This is for
> ModelSim/QuestaSim.


I've done that in the past with Verilog and VCS. VCS compiled the code
into binary and a wrapper was built around it to make it a SWIFT
compatible model. Of course this is architecture and OS dependent.
Don't know if Synopsys provides this for VCS/MX.

Petter
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HT-Lab
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      10-06-2009

"Paul Uiterlinden" <(E-Mail Removed)> wrote in message
news:4acb6817$0$83232$(E-Mail Removed)4all.nl...
> I'm in a situation where some IP written in VHDL must be sent to a customer
> so he can simulate it. Of course we don't want to send the source code.
>
> Normally, what we do is sending pre-compiled libraries, where the the VHDL
> files are compiled using the -nodebug option of vcom. This is for
> ModelSim/QuestaSim.
>
> Now we're facing a customer who does not use ModelSim. Instead, he uses a
> simulator by Cadence (Incisive, I suppose, or ncsim). We do not have
> Cadence tools.
>
> So, what's the best way to cope with this?
>
> The first question is whether ncvhdl has a similar option as the -nodebug
> option of vcom, hiding all internal signals and hierarchy. I have tried to
> find the manual pages of ncvhdl on www.cadence.com but the search results
> from that site are awful.
>
> Second thought is using the new VHDL-2008 `PROTECT keyword. A data sheet on
> the Incisive simulator however does not mention any 2008 support. Is this
> correct?


I would be highly surpriced if they supported VHDL2008, if I remember correctly
it took Synopsys many years to fully support VHDL93 (2001?).

>
> As a last resort we could use some kind of obfuscator like Krypton by Leda
> (if that still exists). But I'm not in favor of that idea.


Obfuscation is very weak, most obfuscators don't change when going though a port
map (they are just glorified find/replace routines).

Some suggestions,

1) Send your customer a synthesised structural netlist (assuming you can
synthesize it)
2) Embed your code in Verilog and use 'protect.
3) Send your customer a prototype board with the design ready to go.
4) Get a Modelsim OEM license for the customer although I am not 100%
sure -nodebug works on an OEM.
5) Translate the code to SystemC using a tool like Carbon, this is a very cool
product but not low-cost.
6) Bite the bullet and send your customer the code + NDA. In this case you might
want to look at adding a digital signature (difficult).

Good luck,

Hans
www.ht-lab.com



>
> Any answers/thoughts are welcome.
> Thanks.
>
> --
> Paul Uiterlinden
> www.aimvalley.nl
> e-mail addres: remove the not.



 
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Mike Treseler
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      10-06-2009
Paul Uiterlinden wrote:
> I'm in a situation where some IP written in VHDL must be sent to a customer
> so he can simulate it. Of course we don't want to send the source code.


And of course the customer wants to try it first.

> Now we're facing a customer who does not use ModelSim. Instead, he uses a
> simulator by Cadence (Incisive, I suppose, or ncsim). We do not have
> Cadence tools. So, what's the best way to cope with this?


I would ask the customer to cover the
cost of the Cadence compilation.
I might have to vpn in, or visit in person.

If the customer were trustworthy,
I might have him purchase the source
at extra cost with some maintenance
included to get it working.


> As a last resort we could use some kind of obfuscator like Krypton by Leda
> (if that still exists). But I'm not in favor of that idea.


That's not much of an option if I don't trust the customer.

-- Mike Treseler
 
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Mike Treseler
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      10-06-2009
Mike Treseler wrote:

> I would ask the customer to cover the
> cost of the Cadence compilation.
> I might have to vpn in, or visit in person.


.... but maybe ncsim's compile does not require a license.

"vcom" runs for free with modelsim last I checked.

-- Mike Treseler
 
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Charles Gardiner
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      10-06-2009
Pity your customer doesn't use Aldec. Both Riviera and ActiveHDL have
VHDL 2008 support (also the `PROTECT option, which I have successfully
used in the way you suggested)

I don't suppose you could persuade your customer to get a trial licence
(21 days) from Aldec for Evaluating your IP.

 
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Paul Uiterlinden
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      10-07-2009
HT-Lab wrote:
>
> Obfuscation is very weak, most obfuscators don't change when going though
> a port map (they are just glorified find/replace routines).
>
> Some suggestions,
>
> 1) Send your customer a synthesised structural netlist (assuming you can
> synthesize it)
> 2) Embed your code in Verilog and use 'protect.
> 3) Send your customer a prototype board with the design ready to go.
> 4) Get a Modelsim OEM license for the customer although I am not 100%
> sure -nodebug works on an OEM.
> 5) Translate the code to SystemC using a tool like Carbon, this is a very
> cool product but not low-cost.
> 6) Bite the bullet and send your customer the code + NDA. In this case you
> might want to look at adding a digital signature (difficult).


Thanks for the suggestions. I'm not quite sure how suggestion #2 should
work. What exactly do you mean with "Embed your code in Verilog"? Surely
creating a Verilog wrapper instantiating a VHDL block and using the `pragma
protect directive does not do anything with the VHDL code? Or am I missing
something?

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
 
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Paul Uiterlinden
Guest
Posts: n/a
 
      10-07-2009
Mike Treseler wrote:

> Mike Treseler wrote:
>
>> I would ask the customer to cover the
>> cost of the Cadence compilation.
>> I might have to vpn in, or visit in person.

>
> ... but maybe ncsim's compile does not require a license.
>
> "vcom" runs for free with modelsim last I checked.


That is still true. The only thing that I do not know is whether ncsim's
compile has a hiding option like the -nodebug option of vcom. And if the
compile uses a license. I guess I should contact Cadence about that.

Thanks to all that replied.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
 
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HT-Lab
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Posts: n/a
 
      10-07-2009

"Paul Uiterlinden" <(E-Mail Removed)> wrote in message
news:4acc53ef$0$83244$(E-Mail Removed)4all.nl...
> HT-Lab wrote:
>>
>> Obfuscation is very weak, most obfuscators don't change when going though
>> a port map (they are just glorified find/replace routines).
>>
>> Some suggestions,
>>
>> 1) Send your customer a synthesised structural netlist (assuming you can
>> synthesize it)
>> 2) Embed your code in Verilog and use 'protect.
>> 3) Send your customer a prototype board with the design ready to go.
>> 4) Get a Modelsim OEM license for the customer although I am not 100%
>> sure -nodebug works on an OEM.
>> 5) Translate the code to SystemC using a tool like Carbon, this is a very
>> cool product but not low-cost.
>> 6) Bite the bullet and send your customer the code + NDA. In this case you
>> might want to look at adding a digital signature (difficult).

>
> Thanks for the suggestions. I'm not quite sure how suggestion #2 should
> work. What exactly do you mean with "Embed your code in Verilog"? Surely
> creating a Verilog wrapper instantiating a VHDL block and using the `pragma
> protect directive does not do anything with the VHDL code? Or am I missing
> something?


No, you are correct,

Hans
www.ht-lab.com


>
> --
> Paul Uiterlinden
> www.aimvalley.nl
> e-mail addres: remove the not.



 
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Paul Uiterlinden
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Posts: n/a
 
      10-07-2009
Paul Uiterlinden wrote:

> Now we're facing a customer who does not use ModelSim. Instead, he uses a
> simulator by Cadence (Incisive, I suppose, or ncsim). We do not have
> Cadence tools.
>
> So, what's the best way to cope with this?


From a Cadence forum that I joined today I got the suggestion to use
ncprotect. It is supposed to be working without the need for a license.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
 
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