The following code compiles OK in Lattice tools but unfortunately I don't have the Xilinx tools on this laptop, will check when back in the office. See if this helps!!

I have added brief comments to the code detailing specific changes.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.all;

-- !!! DON'T USE THESE LIBRARIES - NON STANDARD IEEE LIBS !!!

--use IEEE.STD_LOGIC_ARITH.ALL;

--use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity nhan is

port( a: in std_logic_vector(3 downto 0);

b: in std_logic_vector(3 downto 0);

kq: out std_logic_vector(7 downto 0)

);

end nhan;

architecture Behavioural of nhan is

type mang is array( 0 to 3) of std_logic_vector(7 downto 0);

begin

process(a,b)

variable x: mang;

-- changed type from std_logic_vector to integer as std_logic_vector increments

-- are not possible with the above ieee library standards...

variable t: integer range 0 to 255;

variable y : std_logic_vector(7 downto 0);

begin

for j in 0 to 3 loop

if b(j)='1' then

-- concatenation on std_logic_vectors

y:= "0000" & a;

-- sll takes unsigned arguments, hence convert y to unsigned type.

-- x storage is in std_logic_vector, hence convert std_logic_vector.

x(j) := std_logic_vector(unsigned(y) sll j);

else

x(j):= (others =>'0');

end if;

-- Integer counter, convert std_logic_vector to natural(integer) type..

t := t + to_integer( unsigned( x(j) ) );

end loop;

-- convert integer counter 't' to std_logic_vector

kq<= std_logic_vector( to_unsigned(t,

);

end process;

end;