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Instantiating VHDL/Verilog modules (Generating the top level) usingan XML configuration file

 
 
turituri
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      09-20-2009
Dear All,

I need to find a tool, which can instantiate VHDL/Verilog modules,
using an XML configuration file to define the ports and some constant
parameters (generics), to create a top level.

For example, if I need to instantiate 20 AND gates (or any other IP
that I want to re-use) on the top level, I would somehow create/edit
an XML file, such that the next time I need 30 modules, I will only
change this XML file.

If you have some other suggestion instead of using an XML, you are
more than welcome. All in all, I need to automate the IP re-use.

Regards,
Turituri
 
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HT-Lab
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      09-21-2009

"turituri" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
> Dear All,
>
> I need to find a tool, which can instantiate VHDL/Verilog modules,
> using an XML configuration file to define the ports and some constant
> parameters (generics), to create a top level.
>
> For example, if I need to instantiate 20 AND gates (or any other IP
> that I want to re-use) on the top level, I would somehow create/edit
> an XML file, such that the next time I need 30 modules, I will only
> change this XML file.
>
> If you have some other suggestion instead of using an XML, you are
> more than welcome. All in all, I need to automate the IP re-use.
>
> Regards,
> Turituri


Do a search for IP-XACT+Eclipse, Mentor Graphics HDL-Designer also has an
IP-XACT option and there are more commercial tools.

Hans
www.ht-lab.com




 
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