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clock divider quetion

tia86 tia86 is offline
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Join Date: Sep 2009
Posts: 1
Sorry, the thread title is "clock question" (and i know that the code is useless, is only for undestanding vhdl..)

Why this code is compiled succesfully:
entity yt is
  port (clock50 : IN std_logic;
        clko : OUT std_ulogic
end yt;

architecture dataflow of yt is

	signal clk :  std_logic;
	process (clock50)
	 if (clock50 ='1') THEN
		clk <= '1';
		clk <= '0';
	end if;
	end process;

	 clko <= clk;  
end dataflow;
and if i change " if (clock50 ='1')" into " if (clock50'event and clock50 ='1')" the compiler report "could'nt implement registers for assignemnets on this clock edge"?
They aren't two identical examples? (the sensitivity list has only clock50 so the clock50 rising edge event is captured...).

Last edited by tia86; 09-20-2009 at 01:31 PM..
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debayan_p debayan_p is offline
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Join Date: Jun 2009
Posts: 23

Which compiler are u using ? My ModelSim has never given me such an error !

If u use clk='1' then the sensitivity list will be triggered only when the signal value is true '1'.

But if u use (clk='1' and clk'event), then a rising edge is detected as well as its value is computed.

They say that one should always use the latter condition, if u r putting a clock on the sensitivity list, I donno why, I am not that much experienced VHDL coder. That's the way clock signals are treated.
For any other signal, the check signal='1' or '0' will suffice !

I would be happy if some exp. guy can throw some light on the clock & non-clock signal !
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