Velocity Reviews > VHDL > CPLD Algorithm

# CPLD Algorithm

john
Guest
Posts: n/a

 07-22-2009
Hi All,

An 24 bit ADC is sampling the data from 16 different channels. The
switching frequency of 192 KHz. So, the ADC is sampling at the
frequency 192 Khz / 16 = 12KHz.

Now, I need to store the ADC output data for 16 channels continuously
and convert into I2C protocol and send it to wireless chip. Can any
one proposes any VHDL example, alogorithm or an efficient way to do
this?

Thanks
John

john
Guest
Posts: n/a

 07-22-2009
Hi,

No, There is an 16 channel analog multiplexer that have maximum
switching frequency of 500khz. The output of the multiplexer is
connected to the ADC input. I did not understand the how I will be
hosed and how the ADC will have gooey paste?

JOhn

Marty Ryba
Guest
Posts: n/a

 07-23-2009
"john" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
> No, There is an 16 channel analog multiplexer that have maximum
> switching frequency of 500khz. The output of the multiplexer is
> connected to the ADC input. I did not understand the how I will be
> hosed and how the ADC will have gooey paste?

Well, this is more like sci.electronics.design material as opposed to VHDL,
but Rob's comment has some merit. Unless you do some serious analog
engineering in terms of letting each analog signal settle before the ADC is
clocked (is it a flash ADC, or does the signal have to hold steady for a
bit?), you will get a somewhat gooey mess. A long time ago we did build a
board (running inside an ISA computer) with a couple analog Harris muxes and
a pair of ADCs running at 20 MHz IIRC. Our main problem was that the grad
student who did the PCB layout trusted the autorouter, which put some mux
address lines too close to the analog trace running to the ADC. We were
sampling noisy signals, so we only needed a few bits dynamic range. If you
need high quality sampling as is typical for audio, then you really need to
make sure that signal settles.

-Marty