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coregen-->single port block memory

Roya Roya is offline
Junior Member
Join Date: Jun 2009
Posts: 5
Hi, i got a single port block memory from Xilinx coregen and I initialized it by .coe file. can I read this Rom through this command R<=dout?!
is it clear to read an output port? if not how could I do it?!
I appreciate so much if someone help me.


signal temp: std_logic_vector(7 downto 0);
signal dout : std_logic_vector(7 downto 0);
--component declaration
component rom
clk:in std_logic;
addr:in std_logic_vector(7 downto 0);
dout ut std_logic_vector(7 downto 0));
end component;


--component configuration
memory_instance: rom
port map(
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