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[abidbodal]

Can you add two signals and assign them to another signal of a different size?

Here's part of my code:

signal sv16_wh1_0_cnt :std_logic_vector (15 downto 0);
signal sv16_wh1_90_cnt :std_logic_vector (15 downto 0);
signal sv17_wh1_aver :std_logic_vector (16 downto 0);

--this takes place in a clocked process
sv17_wh1_aver <= (sv16_wh1_0_cnt + sv16_wh1_90_cnt) ;

[jeppe]

Try this:

sv17_wh1_aver <= ('0'&sv16_wh1_0_cnt + '0'&sv16_wh1_90_cnt)

You might be forced to use temp variable of the size 16 downto 0

[abidbodal]

Thanks, that worked