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I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C
I am generating a dpram_32k using Core Generator.
All I can see is 0s (zero) at the output.
How can I see pre-entered initial values in the functional
simulation?


serkan

Serkan wrote:
>
> I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C
> I am generating a dpram_32k using Core Generator.
> All I can see is 0s (zero) at the output.
> How can I see pre-entered initial values in the functional
> simulation?

I would have the testbench write to the ram and read it back.

-- Mike Treseler

On Jun 26, 12:31*am, Mike Treseler <mtrese...@gmail.com> wrote:
> Serkan wrote:
>
> > * I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C
> > * I am generating a dpram_32k using Core Generator.
> > * All I can see is 0s (zero) at the output.
> > * How can I see pre-entered initial values in the functional
> > simulation?
>
> I would have the testbench write to the ram and read it back.
>
> * * * -- Mike Treseler



It takes two much time to simulate using that method.
Is not there any way to do it without the testbench writing the
values?

On 26 June, 06:35, Serkan <ok...@su.sabanciuniv.edu> wrote:
> On Jun 26, 12:31*am, Mike Treseler <mtrese...@gmail.com> wrote:
>
> > Serkan wrote:
>
> > > * I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C
> > > * I am generating a dpram_32k using Core Generator.
> > > * All I can see is 0s (zero) at the output.
> > > * How can I see pre-entered initial values in the functional
> > > simulation?
>
> > I would have the testbench write to the ram and read it back.
>
> > * * * -- Mike Treseler
>
> *It takes two much time to simulate using that method.
> *Is not there any way to do it without the testbench writing the
> values?

Welcome to the world of VHDL simulation.

You could just write an initialisation function to read the values
from a text file.

On 26 Haziran, 10:25, Tricky <Trickyh...@gmail.com> wrote:
> On 26 June, 06:35, Serkan <ok...@su.sabanciuniv.edu> wrote:
>
>
>
> > On Jun 26, 12:31*am, Mike Treseler <mtrese...@gmail.com> wrote:
>
> > > Serkan wrote:
>
> > > > * I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C
> > > > * I am generating a dpram_32k using Core Generator.
> > > > * All I can see is 0s (zero) at the output.
> > > > * How can I see pre-entered initial values in the functional
> > > > simulation?
>
> > > I would have the testbench write to the ram and read it back.
>
> > > * * * -- Mike Treseler
>
> > *It takes two much time to simulate using that method.
> > *Is not there any way to do it without the testbench writing the
> > values?
>
> Welcome to the world of VHDL simulation.
>
> You could just write an initialisation function to read the values
> from a text file.


any guide or link?.

"Serkan" <> wrote in message
news:d0ae7137-f79b-4d1e-b12a-...
On 26 Haziran, 10:25, Tricky <Trickyh...@gmail.com> wrote:
> On 26 June, 06:35, Serkan <ok...@su.sabanciuniv.edu> wrote:
>
>
>
> > On Jun 26, 12:31 am, Mike Treseler <mtrese...@gmail.com> wrote:
>
> > > Serkan wrote:
>
> > > > I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C
> > > > I am generating a dpram_32k using Core Generator.
> > > > All I can see is 0s (zero) at the output.
> > > > How can I see pre-entered initial values in the functional
> > > > simulation?
>
> > > I would have the testbench write to the ram and read it back.
>
> > > -- Mike Treseler
>
> > It takes two much time to simulate using that method.
> > Is not there any way to do it without the testbench writing the
> > values?
>
> Welcome to the world of VHDL simulation.
>
> You could just write an initialisation function to read the values
> from a text file.
>
>
>any guide or link?.

Can't you pre-load it with an MIF file?

Hans
www.ht-lab.com

On 26 Haziran, 12:21, "HT-Lab" <han...@ht-lab.com> wrote:
> "Serkan" <ok...@su.sabanciuniv.edu> wrote in message
>
> news:d0ae7137-f79b-4d1e-b12a-...
> On 26 Haziran, 10:25, Tricky <Trickyh...@gmail.com> wrote:
>
>
>
> > On 26 June, 06:35, Serkan <ok...@su.sabanciuniv.edu> wrote:
>
> > > On Jun 26, 12:31 am, Mike Treseler <mtrese...@gmail.com> wrote:
>
> > > > Serkan wrote:
>
> > > > > I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C
> > > > > I am generating a dpram_32k using Core Generator.
> > > > > All I can see is 0s (zero) at the output.
> > > > > How can I see pre-entered initial values in the functional
> > > > > simulation?
>
> > > > I would have the testbench write to the ram and read it back.
>
> > > > -- Mike Treseler
>




> > > It takes two much time to simulate using that method.
> > > Is not there any way to do it without the testbench writing the
> > > values?
>
> > Welcome to the world of VHDL simulation.
>
> > You could just write an initialisation function to read the values
> > from a text file.
>
> >any guide or link?.
>
> Can't you pre-load it with an MIF file?
>
> Hanswww.ht-lab.com



I tried using a mif file but all I can see is zeros at the output when
I do functional simulation.
But if I do timing simulation then I can see correct data values.
Very strange I must admit.

"Serkan" <> wrote in message
news:c0899c4d-dd8b-4c9b-84d7-...
> On 26 Haziran, 12:21, "HT-Lab" <han...@ht-lab.com> wrote:
>> "Serkan" <ok...@su.sabanciuniv.edu> wrote in message
...
>>
>> > You could just write an initialisation function to read the values
>> > from a text file.
>>
>> >any guide or link?.
>>
>> Can't you pre-load it with an MIF file?
>>
>> Hanswww.ht-lab.com
>
>
>
> I tried using a mif file but all I can see is zeros at the output when
> I do functional simulation.
> But if I do timing simulation then I can see correct data values.
> Very strange I must admit.
>
Looks like a timing or delta-delay issue.

Have a look in the manual to see how to use the list window.

Hans
www.ht-lab.com

On 26 Haziran, 14:18, "HT-Lab" <han...@ht-lab.com> wrote:
> "Serkan" <ok...@su.sabanciuniv.edu> wrote in message
>
> news:c0899c4d-dd8b-4c9b-84d7-...
>
> > On 26 Haziran, 12:21, "HT-Lab" <han...@ht-lab.com> wrote:
> >> "Serkan" <ok...@su.sabanciuniv.edu> wrote in message
> ..
>
> >> > You could just write an initialisation function to read the values
> >> > from a text file.
>
> >> >any guide or link?.
>
> >> Can't you pre-load it with an MIF file?
>
> >> Hanswww.ht-lab.com
>
> > I tried using a mif file but all I can see is zeros at the output when
> > I do functional simulation.
> > But if I do timing simulation then I can see correct data values.
> > Very strange I must admit.
>
> Looks like a timing or delta-delay issue.
>
> Have a look in the manual to see how to use the list window.
>
> Hanswww.ht-lab.com


It is not related to timing or delta delay issue
Searched other forums. People are wining about the same problem.
I even saw other Mike Treseler posts.
Some say, a modelsim bug. If I manage to do it, I will post the
solution.

thank you all for your answers.

Serkan wrote:

> It takes two much time to simulate using that method.
> Is not there any way to do it without the testbench writing the
> values?

Is your intent to test the ram design?
Finding the init data does not prove
that the ram works.

-- Mike Treseler