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pre-initialized dpram functional simulation

 
 
Serkan
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      06-25-2009


I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C
I am generating a dpram_32k using Core Generator.
All I can see is 0s (zero) at the output.
How can I see pre-entered initial values in the functional
simulation?


serkan
 
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Mike Treseler
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      06-25-2009
Serkan wrote:
>
> I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C
> I am generating a dpram_32k using Core Generator.
> All I can see is 0s (zero) at the output.
> How can I see pre-entered initial values in the functional
> simulation?


I would have the testbench write to the ram and read it back.

-- Mike Treseler
 
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Serkan
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      06-26-2009
On Jun 26, 12:31*am, Mike Treseler <(E-Mail Removed)> wrote:
> Serkan wrote:
>
> > * I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C
> > * I am generating a dpram_32k using Core Generator.
> > * All I can see is 0s (zero) at the output.
> > * How can I see pre-entered initial values in the functional
> > simulation?

>
> I would have the testbench write to the ram and read it back.
>
> * * * -- Mike Treseler




It takes two much time to simulate using that method.
Is not there any way to do it without the testbench writing the
values?
 
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Tricky
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      06-26-2009
On 26 June, 06:35, Serkan <(E-Mail Removed)> wrote:
> On Jun 26, 12:31*am, Mike Treseler <(E-Mail Removed)> wrote:
>
> > Serkan wrote:

>
> > > * I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C
> > > * I am generating a dpram_32k using Core Generator.
> > > * All I can see is 0s (zero) at the output.
> > > * How can I see pre-entered initial values in the functional
> > > simulation?

>
> > I would have the testbench write to the ram and read it back.

>
> > * * * -- Mike Treseler

>
> *It takes two much time to simulate using that method.
> *Is not there any way to do it without the testbench writing the
> values?


Welcome to the world of VHDL simulation.

You could just write an initialisation function to read the values
from a text file.
 
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Serkan
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      06-26-2009
On 26 Haziran, 10:25, Tricky <(E-Mail Removed)> wrote:
> On 26 June, 06:35, Serkan <(E-Mail Removed)> wrote:
>
>
>
> > On Jun 26, 12:31*am, Mike Treseler <(E-Mail Removed)> wrote:

>
> > > Serkan wrote:

>
> > > > * I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C
> > > > * I am generating a dpram_32k using Core Generator.
> > > > * All I can see is 0s (zero) at the output.
> > > > * How can I see pre-entered initial values in the functional
> > > > simulation?

>
> > > I would have the testbench write to the ram and read it back.

>
> > > * * * -- Mike Treseler

>
> > *It takes two much time to simulate using that method.
> > *Is not there any way to do it without the testbench writing the
> > values?

>
> Welcome to the world of VHDL simulation.
>
> You could just write an initialisation function to read the values
> from a text file.



any guide or link?.

 
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HT-Lab
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      06-26-2009

"Serkan" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
On 26 Haziran, 10:25, Tricky <(E-Mail Removed)> wrote:
> On 26 June, 06:35, Serkan <(E-Mail Removed)> wrote:
>
>
>
> > On Jun 26, 12:31 am, Mike Treseler <(E-Mail Removed)> wrote:

>
> > > Serkan wrote:

>
> > > > I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C
> > > > I am generating a dpram_32k using Core Generator.
> > > > All I can see is 0s (zero) at the output.
> > > > How can I see pre-entered initial values in the functional
> > > > simulation?

>
> > > I would have the testbench write to the ram and read it back.

>
> > > -- Mike Treseler

>
> > It takes two much time to simulate using that method.
> > Is not there any way to do it without the testbench writing the
> > values?

>
> Welcome to the world of VHDL simulation.
>
> You could just write an initialisation function to read the values
> from a text file.
>
>
>any guide or link?.


Can't you pre-load it with an MIF file?

Hans
www.ht-lab.com




 
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Serkan
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      06-26-2009
On 26 Haziran, 12:21, "HT-Lab" <(E-Mail Removed)> wrote:
> "Serkan" <(E-Mail Removed)> wrote in message
>
> news:(E-Mail Removed)...
> On 26 Haziran, 10:25, Tricky <(E-Mail Removed)> wrote:
>
>
>
> > On 26 June, 06:35, Serkan <(E-Mail Removed)> wrote:

>
> > > On Jun 26, 12:31 am, Mike Treseler <(E-Mail Removed)> wrote:

>
> > > > Serkan wrote:

>
> > > > > I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C
> > > > > I am generating a dpram_32k using Core Generator.
> > > > > All I can see is 0s (zero) at the output.
> > > > > How can I see pre-entered initial values in the functional
> > > > > simulation?

>
> > > > I would have the testbench write to the ram and read it back.

>
> > > > -- Mike Treseler

>





> > > It takes two much time to simulate using that method.
> > > Is not there any way to do it without the testbench writing the
> > > values?

>
> > Welcome to the world of VHDL simulation.

>
> > You could just write an initialisation function to read the values
> > from a text file.

>
> >any guide or link?.

>
> Can't you pre-load it with an MIF file?
>
> Hanswww.ht-lab.com




I tried using a mif file but all I can see is zeros at the output when
I do functional simulation.
But if I do timing simulation then I can see correct data values.
Very strange I must admit.





 
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HT-Lab
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      06-26-2009

"Serkan" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
> On 26 Haziran, 12:21, "HT-Lab" <(E-Mail Removed)> wrote:
>> "Serkan" <(E-Mail Removed)> wrote in message

...
>>
>> > You could just write an initialisation function to read the values
>> > from a text file.

>>
>> >any guide or link?.

>>
>> Can't you pre-load it with an MIF file?
>>
>> Hanswww.ht-lab.com

>
>
>
> I tried using a mif file but all I can see is zeros at the output when
> I do functional simulation.
> But if I do timing simulation then I can see correct data values.
> Very strange I must admit.
>

Looks like a timing or delta-delay issue.

Have a look in the manual to see how to use the list window.

Hans
www.ht-lab.com


 
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Serkan
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      06-26-2009
On 26 Haziran, 14:18, "HT-Lab" <(E-Mail Removed)> wrote:
> "Serkan" <(E-Mail Removed)> wrote in message
>
> news:(E-Mail Removed)...
>
> > On 26 Haziran, 12:21, "HT-Lab" <(E-Mail Removed)> wrote:
> >> "Serkan" <(E-Mail Removed)> wrote in message

> ..
>
> >> > You could just write an initialisation function to read the values
> >> > from a text file.

>
> >> >any guide or link?.

>
> >> Can't you pre-load it with an MIF file?

>
> >> Hanswww.ht-lab.com

>
> > I tried using a mif file but all I can see is zeros at the output when
> > I do functional simulation.
> > But if I do timing simulation then I can see correct data values.
> > Very strange I must admit.

>
> Looks like a timing or delta-delay issue.
>
> Have a look in the manual to see how to use the list window.
>
> Hanswww.ht-lab.com



It is not related to timing or delta delay issue
Searched other forums. People are wining about the same problem.
I even saw other Mike Treseler posts.
Some say, a modelsim bug. If I manage to do it, I will post the
solution.

thank you all for your answers.
 
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Mike Treseler
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      06-26-2009
Serkan wrote:

> It takes two much time to simulate using that method.
> Is not there any way to do it without the testbench writing the
> values?


Is your intent to test the ram design?
Finding the init data does not prove
that the ram works.

-- Mike Treseler
 
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