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Re: True dual-port RAM in VHDL: XST question

 
 
Muzaffer Kal
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      06-24-2009
On Wed, 24 Jun 2009 16:27:30 +0100, "Fredxx" <(E-Mail Removed)> wrote:
>The asynchronous memory is an array of flip-flops rather than a memory, but
>that's a mute point. It does both synthesise and simulate in Xilinx ISE
>tools.
>

Flip-flops need a clock to function. How do you write to them without
a clock to implement asynchronous memory (which by definition doesn't
have it?). You can use an array of latches as opposed to flip-flops
but timing latches is quite difficult especially in an fpga context
where tools are really not geared towards it. You maybe able to
synthesize it in ISE and the original code simulates for sure but have
you tried a back-annotated gate level simulation? It would be an
interesting challenge to get it to work fully unless your read/write
pulse widths and separations are extremely conservative.
One last to remember is that there are a lot fewer slice registers
(from which latches are made) than memory bits in an FPGA so you're
quite limited in how much async memory of this type you can make.
---
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
 
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Andy
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      06-24-2009
On Jun 24, 6:15*am, Jonathan Bromley <(E-Mail Removed)>
wrote:
> In truth the "correct" solution would be to write the whole thing
> as a single process with two clocks:
>
> * process (clock0, clock1)
> * * variable mem: t_mem;
> * begin
> * * if rising_edge(clock0) then
> * * * if we0 = '1' then
> * * * * mem(a0) := wd0;
> * * * end if;
> * * end if;
> * * if rising_edge(clock1) then
> * * * if we1 = '1' then
> * * * * mem(a1) := wd1;
> * * * end if;
> * * end if;
> * * ...
>
> But I suspect synthesis tools would chuck that overboard
> without a second thought.


Current synthesis tools would probably have an issue with this, but
there's no good reason for it. DDR synthesis (though not the same as
independent clock, dual port memories) needs it anyway. Some synthesis
tools support dual clock processes, just not writes to the same var/
sig on both clocks. The only time this example does not behave like a
true dual clock/port ram is when two writes are attempted to the same
address at exactly the same time, which is not even defined for the
real HW. Good system design makes that case meaningless anyway.

Andy
 
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Muzaffer Kal
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      06-24-2009
On Wed, 24 Jun 2009 18:57:29 +0100, Jonathan Bromley
<(E-Mail Removed)> wrote:

>I'm trying to assemble a complete and accurate list
>of the _synthesizable_ templates for all common types
>of FPGA memory, and I have discovered a template
>that synthesizes to dual-clock RAM in two FPGA
>vendors' tools but is a complete nonsense for
>simulation. I want to know why this has happened,
>what we can do about it, and why the vendors haven't
>already been beaten to pulp over it by users.


Originally coming from ASIC side I find this incredible but it seems
that majority of people doing FPGA design don't simulate. I was at an
FPGA infomercial the other day about two new device families coming
out from a vendor to stay nameless and only %20 or so people raised
their hands when asked this question. This might explain how these
templates survived as is for such a long time.
---
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
 
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Mike Treseler
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      06-24-2009
Jonathan Bromley wrote:

> I'm trying to assemble a complete and accurate list
> of the _synthesizable_ templates for all common types
> of FPGA memory, and I have discovered a template
> that synthesizes to dual-clock RAM in two FPGA
> vendors' tools but is a complete nonsense for
> simulation. I want to know why this has happened,
> what we can do about it, and why the vendors haven't
> already been beaten to pulp over it by users.


This has happen because the majority of FPGA
designers prefer to wire together blocks
by others, and verify on the bench using
trial and error synthesis.

The silly dual clock RAM model is ignored
not because it is silly, but because
a vendor netlist is preferred to RTL
to get at all the asynchronous black magic.

What to do? I stick with single clock RAMs
and arbitrate synchronously.

-- Mike Treseler


 
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Andy Peters
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      06-24-2009
On Jun 24, 10:57*am, Jonathan Bromley <(E-Mail Removed)>
wrote:
> I'm trying to assemble a complete and accurate list
> of the _synthesizable_ templates for all common types
> of FPGA memory, and I have discovered a template
> that synthesizes to dual-clock RAM in two FPGA
> vendors' tools but is a complete nonsense for
> simulation. *I want to know why this has happened,
> what we can do about it, and why the vendors haven't
> already been beaten to pulp over it by users.


The vendors say, "Instantiate the component from the library," which
neatly sidesteps the difficult work of actually enabling such
inference.

-a
 
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Alex
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      06-25-2009
On Jun 24, 10:57*am, Jonathan Bromley <(E-Mail Removed)>
wrote:
> On Wed, 24 Jun 2009 08:31:26 -0700 (PDT), Sandro wrote:
> >If you are curious please take a look to the vhdl VITAL
> >simulations sources...

>
> I know about the vendor-provided simulation models,
> which are fine pieces of work that do their job well.
> But they are completely irrelevant both to my original
> problem and to the issue I asked about. *
>
> I'm trying to assemble a complete and accurate list
> of the _synthesizable_ templates for all common types
> of FPGA memory, and I have discovered a template
> that synthesizes to dual-clock RAM in two FPGA
> vendors' tools but is a complete nonsense for
> simulation. *I want to know why this has happened,
> what we can do about it, and why the vendors haven't
> already been beaten to pulp over it by users.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> (E-Mail Removed)://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.



The truth is that current FPGA Synthesis tools quite often do a poor
job (not counting trivial cases here) in inference of FPGA vendors'
macros. From the other hand FPGA vendors want users to instantiate
their macros (and so to be locked into their devices) and make it very
easy to configure and generate the code for instantiation using
proprietary vendor tools.
So majority of users prefers to instantiate the macros as a better
alternative to make the Synthesis tools infer the necessary structure
(and lose sometimes days on debugging different synthesis attributes,
directives etc...)
Just wanted to offer a possible explanation in answer to your
question, Jonathan :^)

Theoretically, independent FPGA synthesis tools vendors (Mentor,
Synopsys) should be interested for users to create a vendor
independent code. This way they'll have a much stronger case for multi-
vendor tools...

Alex Yourovski
 
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Martin Thompson
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      06-25-2009
Jonathan Bromley <(E-Mail Removed)> writes:

> I completely agree. One of the side-effects of the
> survey I'm doing will probably be that I'll log requests
> for exactly this feature with all the synthesis vendors.
> I don't hold out much hope, though. Support welcomed


You have mine!

And thanks for sharing the results of your investigations with us all!

Cheers,
Martin

--
http://www.velocityreviews.com/forums/(E-Mail Removed)
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
 
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Nial Stewart
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      06-25-2009
> Originally coming from ASIC side I find this incredible but it seems
> that majority of people doing FPGA design don't simulate. I was at an
> FPGA infomercial the other day about two new device families coming
> out from a vendor to stay nameless and only %20 or so people raised
> their hands when asked this question. This might explain how these
> templates survived as is for such a long time.



Do you mean don't simulate the P&R'd design, or not at all?



Nial.


 
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sleeman
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      06-25-2009
On Jun 25, 6:55*am, "Nial Stewart"
<nial*(E-Mail Removed) > wrote:
> > Originally coming from ASIC side I find this incredible but it seems
> > that majority of people doing FPGA design don't simulate. I was at an
> > FPGA infomercial the other day about two new device families coming
> > out from a vendor to stay nameless and only %20 or so people raised
> > their hands when asked this question. This might explain how these
> > templates survived as is for such a long time.

>
> Do you mean don't simulate the P&R'd design, or not at all?
>
> Nial.


This thread has brought up several very interesting themes. I'd like
to add my two cents to each.

1) Synthesis templates for RAMS. I think what Jonathan is doing is a
great idea. I'd love to see a better definition of what cross-device
code patterns are safe to use and supported by which tools. From
experience, I can say that I've done it right for a few key designs,
and managed to leverage off of that by wrapping this inference in an
entity, giving me a device-independent (more-or-less) codebase but
still requiring structural coding around the RAM. It's not ideal by a
long shot. But by enforcing good version control discipline through
the organization and introducing a mindset that says "don't fiddle
around with a perfectly good library module, use it as-is or not at
all", we have managed to reduce the number of times designers sit
there, asking the same questions: "I only changed one line of code;
why did it start making distributed RAM? What were those attributes
again? When I don't use the read port how do I stop the synthesizer
from complaining?" and so on and so on.

2) Clocks versus asynchronous logic. My view of this is that clocks
are both an obvious physical thing (as anyone who flies a scope for
living well knows) as well as an abstraction. This abstraction is
what constitutes the "contract", or point of demarcation between high-
level circuit digital designer, and the guy who actually codes the
gate-level RAM and control logic. The job of the low-level transistor
guy is to provide a circuit that acts as if the clock abstraction is a
true representation of what actually happens inside. He may use flops,
latches, vernier timing thingies, or whatever the heck he needs. But
he *must* obey the clock-concept contract. The job of the high-level
(FPGA application developer) is to make use of the clock concept
abstraction in order to make his design synchronous, which implies
robustness, maintainability, and all the other virtues that regular
posters here know so well.

3) People who don't do simulation? Definitely. I've help manage the
change in an organization growing from a couple of FPGA guys to a
fairly well-oiled FPGA talent pool with established version control,
substantial as-is module re-use, and an ingrained mindset that a
modules doesn't get released without a scripted, regressionable
testbench. They're two points at opposite ends of a continuum of
process, but I see a lot of real work in industry done at both ends.

The "garage shop" FPGA approach typically has some guys who learned
VHDL in school, then got thrown into the deep end alone, or who "came
up through the ranks" from CPLDs and board design. No VC, no software
techniques, no libraries, packages, functions or elegant code in the
source. Hack job, in short. Two of these guys working on the same
project may often be running different tool versions, and not even be
able to load the design as-is from the other guy's sources, without a
lot of manual GUI fiddling to reset paths, manually link in the right
libraries, and so on. There's little chance of even building the same
design twice in a row. These are the guys who throw their bitfile onto
the board, and if it doesn't work, start writing some testbenches
(aww, do I *have* to do that... what a pain). They don't want to
simulate because its too hard/too long to sim the whole chip, and
because there's poor structure and/or modularity in their own code to
begin with, so it's also too hard to isolate a portion and make a
simple test for it, too.

The "pro" is at the other end of the continuum. Most of the regular
posters here try to answer the "garage guys" with answers that will
point them in the direction of becoming a "pro". It's a lot more
work, but there's a lot of benefit to being able to release a chip
that you know that anyone on your team can build again, bit/UCF/source-
accurately, when you're on vacation.

Of course, some "pros" work in garage shops. But the Big Tool (Big
Two?) vendors tend to cater most of their tools to the garage shop
guys. Everything can be set by clicking on a GUI button. Everything
about a project is stored in unreadable binary files. They try to
force you into their half-assed version control scheme, if they offer
one at all. How are you ever going to share designs or document them
for the future that way? And all of the "sex appeal" about the new
devices is put into the GUI, the new buttons that you can click on,
and the new auto-wizards (that don't usually have a mode to generate
output from anything other than unreliable, unrepeatable user mouse
clicks). ( I tend to think of this emphasis on sexy GUI tools leading
then to bad project practices as being akin to drug dealers pushing
crack in the schoolyards, but that would get me in trouble with my
local FAEs so I'll refrain

Don't get me wrong... I had a lot of fun as a garage guy myself. I
built some pretty damn fine hardware "back in the day" before I even
had the option of simulating my code. But I agree, there are still a
lot of guys who view testbenches and simulation as something painful
and only to be done if really necessary. In truth, it's like pretty
much everything else in life: you get out more when you put in more
work.

OK, I'm done ranting now

- Kenn
 
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rickman
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      06-25-2009
On Jun 24, 2:11*pm, Muzaffer Kal <(E-Mail Removed)> wrote:
> On Wed, 24 Jun 2009 18:57:29 +0100, Jonathan Bromley
>
> <(E-Mail Removed)> wrote:
> >I'm trying to assemble a complete and accurate list
> >of the _synthesizable_ templates for all common types
> >of FPGA memory, and I have discovered a template
> >that synthesizes to dual-clock RAM in two FPGA
> >vendors' tools but is a complete nonsense for
> >simulation. *I want to know why this has happened,
> >what we can do about it, and why the vendors haven't
> >already been beaten to pulp over it by users.

>
> Originally coming from ASIC side I find this incredible but it seems
> that majority of people doing FPGA design don't simulate. I was at an
> FPGA infomercial the other day about two new device families coming
> out from a vendor to stay nameless and only %20 or so people raised
> their hands when asked this question.


I missed something. What question exactly?

Rick
 
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