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Power up state

 
 
Alfonso Baz
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      06-21-2009
Hi all, I've just started learning VHDL so some of my questions may seem
rudimentary...

Is there any way of guaranteeing the state of an output pin on power up?

Is it done from the VHDL or is it a constraint thing or perhaps something
else

Cheers
Alf



 
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backhus
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      06-22-2009
On 21 Jun., 04:40, "Alfonso Baz" <(E-Mail Removed)> wrote:
> Hi all, I've just started learning VHDL so some of my questions may seem
> rudimentary...
>
> Is there any way of guaranteeing the state of an output pin on power up?
>
> Is it done from the VHDL or is it a constraint thing or perhaps something
> else
>
> Cheers
> Alf


Hi Alfonso,
from VHDL point of view, registered outputs can have an asynchronous
reset to get an initial state. Combinatorical signals immediatlely
(that is after their delay) react to their inputs. you may create some
output enable with an and gate or a tristate bufffer to control the
power up behavior.

The other thing is physics. The behavior of the target architecture.
You have to read the datasheet, for CPLD and FPGAs and ask the fab if
you are going to design for ASICs.

The power on behavior depends on the used technology. e.g. most SRAM
based FPGAs hold their I/Os in the tristate while loading their
bitsreams and provide an internal reset signal (and locked signals for
PLLs DCMs etc) to tell the user circuit when to start.

Have a nice synthesis
Eilert
 
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Alfonso Baz
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      06-23-2009
Thanks for the reply Eilert, you've pointed me in right direction.
I've done some reading and found that for the CPLD (XC95144XL) it has two
power supplies
One for the internals (Vccint) and one for the IO buffers (Vccio).

You were correct with the tri-state start up, the documentation reveals it
also has a weak pullup.

The recommended way to power up with a known state is to first apply power
to Vccint enabling
the logic to sort itself out and then Vccio.

If both a powered up simultaneously the documentation states that for this
CPLD device, an output
that is meant to be low on power up will exhibit a "glitch"

Cheers
Alfonso

"backhus" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
> On 21 Jun., 04:40, "Alfonso Baz" <(E-Mail Removed)> wrote:
>> Hi all, I've just started learning VHDL so some of my questions may seem
>> rudimentary...
>>
>> Is there any way of guaranteeing the state of an output pin on power up?
>>
>> Is it done from the VHDL or is it a constraint thing or perhaps something
>> else
>>
>> Cheers
>> Alf

>
> Hi Alfonso,
> from VHDL point of view, registered outputs can have an asynchronous
> reset to get an initial state. Combinatorical signals immediatlely
> (that is after their delay) react to their inputs. you may create some
> output enable with an and gate or a tristate bufffer to control the
> power up behavior.
>
> The other thing is physics. The behavior of the target architecture.
> You have to read the datasheet, for CPLD and FPGAs and ask the fab if
> you are going to design for ASICs.
>
> The power on behavior depends on the used technology. e.g. most SRAM
> based FPGAs hold their I/Os in the tristate while loading their
> bitsreams and provide an internal reset signal (and locked signals for
> PLLs DCMs etc) to tell the user circuit when to start.
>
> Have a nice synthesis
> Eilert



 
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