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VHDL - intermediate signal simulation |
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06-19-2009, 08:01 AM
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#1 |
intermediate signal simulation
hi all
i want to see the waveforms of intermediate signals in the test bench simulation window. it only shows the signals declared in ports but not intermidate ones. pls let me know how can i see those signals. i am new to fpga world! sshiremath2000@gmail.com |
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