VHDL signed addition does not yield correct result

Hello,

I have a piece of VHDL code that does signed addition of an unsigned number and a signed number. However the result is always a sum of the two magnitudes irrespective of the sign of the second operand (I expect a difference when sign is 1)

Could you please tell me what I am doing wrong. Here is my code:

include IEEE.numeric_std.all;
op1: unsigned (7 downto 0);
op2: signed (7 downto 0);
op3: signed(6 downto 0);
result: signed (41 downto 0);
sum: signed(7 downto 0);

result <= mult3 + mult2 + T1; (result is negative number represented as 2's complement)

op2 <= resize(result, "8"); -- should yield a negative number (ignore quotes, I had to put that there to defeat the smiley showing up)

op3 <= shift_right(op2, 1); -- should yield a negative number
sum <= op1(7) & (signed(op1(6 downto 0)) + op3);

If op1 = 'h0C and op3 = 'h62, I get sum = 'h6E which is not right because op3 is negative.

Thanks much for your help.

pap74