Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Want flag to keep value through all states

Reply
Thread Tools

Want flag to keep value through all states

 
 
Shannon
Guest
Posts: n/a
 
      06-15-2009
I am using a single-process state-machine style of coding. I have a
flag that gets set or cleared in one state. I want it to keep
whatever value that is throughout the rest of the state machine until
the machine returns to that state. What is the correct way of doing
this?

Please note that I am not referring to a "default" state. That much I
understand. I just want the flag to be set once and then stay that
way regardless of the condition that set it changing later.

Process (clk)
begin
if rising_edge(clk) then
case state
when one =>
flag <= input;
...
when two =>
if flag = '1' then
....
else
....
etc...

Thanks,
Shannon
 
Reply With Quote
 
 
 
 
Shannon
Guest
Posts: n/a
 
      06-15-2009
On Jun 15, 1:34*pm, Shannon <(E-Mail Removed)> wrote:
> I am using a single-process state-machine style of coding. *I have a
> flag that gets set or cleared in one state. *I want it to keep
> whatever value that is throughout the rest of the state machine until
> the machine returns to that state. *What is the correct way of doing
> this?
>
> Please note that I am not referring to a "default" state. *That much I
> understand. *I just want the flag to be set once and then stay that
> way regardless of the condition that set it changing later.
>
> Process (clk)
> begin
> * if rising_edge(clk) then
> * * case state
> * * * when one =>
> * * * * *flag <= input;
> * * * * *...
> * * * when two =>
> * * * * *if flag = '1' then
> * * * * * ....
> * * * * *else
> * * * * *....
> etc...
>
> Thanks,
> Shannon


I'm suffering post traumatic "send" disorder....

I'm betting that I don't have to do anything since it is in a clocked
process and will become a register.

Shannon
 
Reply With Quote
 
 
 
 
Dave
Guest
Posts: n/a
 
      06-15-2009
On Jun 15, 4:34*pm, Shannon <(E-Mail Removed)> wrote:
> I am using a single-process state-machine style of coding. *I have a
> flag that gets set or cleared in one state. *I want it to keep
> whatever value that is throughout the rest of the state machine until
> the machine returns to that state. *What is the correct way of doing
> this?
>
> Please note that I am not referring to a "default" state. *That much I
> understand. *I just want the flag to be set once and then stay that
> way regardless of the condition that set it changing later.
>
> Process (clk)
> begin
> * if rising_edge(clk) then
> * * case state
> * * * when one =>
> * * * * *flag <= input;
> * * * * *...
> * * * when two =>
> * * * * *if flag = '1' then
> * * * * * ....
> * * * * *else
> * * * * *....
> etc...
>
> Thanks,
> Shannon


If you simply don't assign the signal's value in those states where
the signal should remain unchanged, then the value will remain the
same until the next clock tick. The synthesizer will implement this by
making the clock enable for the signal's register '0' for those states
where the signal is not assigned. This is one of the nice things about
single-process state machines.

Dave
 
Reply With Quote
 
Mike Treseler
Guest
Posts: n/a
 
      06-16-2009
Dave wrote:

> If you simply don't assign the signal's value in those states where
> the signal should remain unchanged, then the value will remain the
> same until the next clock tick. The synthesizer will implement this by
> making the clock enable for the signal's register '0' for those states
> where the signal is not assigned. This is one of the nice things about
> single-process state machines.


Yes.
Describing changes takes less text
than describing the full state and output.

It is unfortunate that asynchronous processes
and the default assignments they require,
are so well covered in vhdl instruction.

Some designers retain this verbose
style in all cases, out of habit.

-- Mike Treseler

 
Reply With Quote
 
Andy
Guest
Posts: n/a
 
      06-16-2009
On Jun 16, 12:22*pm, Mike Treseler <(E-Mail Removed)> wrote:
> Dave wrote:
> > If you simply don't assign the signal's value in those states where
> > the signal should remain unchanged, then the value will remain the
> > same until the next clock tick. The synthesizer will implement this by
> > making the clock enable for the signal's register '0' for those states
> > where the signal is not assigned. This is one of the nice things about
> > single-process state machines.

>
> Yes.
> Describing changes takes less text
> than describing the full state and output.
>
> It is unfortunate that asynchronous processes
> and the default assignments they require,
> are so well covered in vhdl instruction.
>
> Some designers retain this verbose
> style in all cases, out of habit.
>
> * * * * -- Mike Treseler


What's worse, most texts that promote dual processes also don't
promote the best way to avoid latches in the combinatorial processes:
default assignments right up front in the process. With those, you
have your choice of default signal behavior being unchanged, set or
reset for each signal. Most texts try to focus on an else for every
if, and complete assignment lists in every state, both of which are
much harder to write, read and update/maintain.

You still have all the default behavior choices with a single clocked
process, which is much better in the first place.

Andy
 
Reply With Quote
 
Shannon
Guest
Posts: n/a
 
      06-16-2009
On Jun 16, 10:36*am, Andy <(E-Mail Removed)> wrote:
> On Jun 16, 12:22*pm, Mike Treseler <(E-Mail Removed)> wrote:
>
>
>
> > Dave wrote:
> > > If you simply don't assign the signal's value in those states where
> > > the signal should remain unchanged, then the value will remain the
> > > same until the next clock tick. The synthesizer will implement this by
> > > making the clock enable for the signal's register '0' for those states
> > > where the signal is not assigned. This is one of the nice things about
> > > single-process state machines.

>
> > Yes.
> > Describing changes takes less text
> > than describing the full state and output.

>
> > It is unfortunate that asynchronous processes
> > and the default assignments they require,
> > are so well covered in vhdl instruction.

>
> > Some designers retain this verbose
> > style in all cases, out of habit.

>
> > * * * * -- Mike Treseler

>
> What's worse, most texts that promote dual processes also don't
> promote the best way to avoid latches in the combinatorial processes:
> default assignments right up front in the process. With those, you
> have your choice of default signal behavior being unchanged, set or
> reset for each signal. Most texts try to focus on an else for every
> if, and complete assignment lists in every state, both of which are
> much harder to write, read and update/maintain.
>
> You still have all the default behavior choices with a single clocked
> process, which is much better in the first place.
>
> Andy


thanks for the help. I suspected the answer moments after I pressed
send. I used to be a two-process person but you guys convinced me
otherwise. I never was a three-process person.

Shannon
 
Reply With Quote
 
Mike Treseler
Guest
Posts: n/a
 
      06-18-2009
Shannon wrote:

> I'm suffering post traumatic "send" disorder....


And yet the "send" button is the source of all enlightenment
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
How keep python socket alive for ever by setting Keep alive flag. hisan Python 1 06-25-2012 05:30 PM
VHDL to Control HD44780 (want to read busy flag) BlackHelicopter VHDL 0 12-09-2010 05:52 AM
anywhere to get all US states + counties data Bobby Edward ASP .Net 3 10-28-2008 01:04 PM
A gridview event/method to capture all checkbox.check states in this BoundColumn and Item_Bound grid? hazz ASP .Net 0 05-03-2006 06:10 PM
Onchange of dropdownlist say "country" loaded,it must load all "states" for that country in another drop downlist. S.Guhananth ASP .Net 1 04-30-2005 12:01 PM



Advertisments