About Altera patent application "Logic Cell Supporting Addition ofThree Binary Words"

Hi,
I recently read Altera Stratix II, III and IV device handbook and
found its 3-bit addition circuit is really a genius invention. But I
was surprised to find that Altera patent application "Logic Cell
Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has
not been approved to be a patent so far today, even though many Altera
later patent applications based on the invention have been approved
for U.S. patents.

Is anyone knowledgable about the patent application willing to
transfer the patent application context to me and disclose why it
hasn't been approved as a U.S. patent.

My guess is it may never be approved by U.S. Patent Office to be a
patent, the reason is not its novelty violation, but its context
didn't disclose enough information about the 3-bit addition circuit, a
requirement for any patent application to be approved to be a U.S.
patent. At least those skilled in the art cannot get the idea what is
done within its circuit having an encircled '+' with 3 inputs and 2
outputs.

Altera another sister patent application "Arithmetic Structure is for
Programmable Logic Device" filed on Oct. 23, 2003 has the same fate.

Thank you.

Weng

Weng Tianxiang

On Jun 14, 1:21*pm, Weng Tianxiang <wtx...@gmail.com> wrote:
> Hi,
> I recently read Altera Stratix II, III and IV device handbook and
> found its 3-bit addition circuit is really a genius invention. But I
> was surprised to find that Altera patent application "Logic Cell
> Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has
> not been approved to be a patent so far today, even though many Altera
> later patent applications based on the invention have been approved
> for U.S. patents.
>
> Is anyone knowledgable about the patent application willing to
> transfer the patent application context to me and disclose why it
> hasn't been approved as a U.S. patent.
>
> My guess is it may never be approved by U.S. Patent Office to be a
> patent, the reason is not its novelty violation, but its context
> didn't disclose enough information about the 3-bit addition circuit, a
> requirement for any patent application to be approved to be a U.S.
> patent. At least those skilled in the art cannot get the idea what is
> done within its circuit having an encircled '+' with 3 inputs and 2
> outputs.
>
> Altera another sister patent application "Arithmetic Structure is for
> Programmable Logic Device" filed on Oct. 23, 2003 has the same fate.
>
> Thank you.
>
> Weng

I don't know why Altera wouldn't disclose info on the structure being
used in a device. It is relatively inexpensive to reverse engineer a
chip, so if it is not disclosed in a patent, it is not protected and
is vulnerable to being copied.

What exactly *does* the patent claim? Maybe the design inside the
circled + is not really novel and only the design around the circle is
novel enough to be patented?

In general, I think a three in put adder is *very useful*. I've never
seen such a circuit, I guess the carry chain has multiple bits, eh?

Rick

rickman

On Jun 15, 4:36*am, rickman <gnu...@gmail.com> wrote:
> On Jun 14, 1:21*pm, Weng Tianxiang <wtx...@gmail.com> wrote:
>
>
>
>
>
> > Hi,
> > I recently read Altera Stratix II, III and IV device handbook and
> > found its 3-bit addition circuit is really a genius invention. But I
> > was surprised to find that Altera patent application "Logic Cell
> > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has
> > not been approved to be a patent so far today, even though many Altera
> > later patent applications based on the invention have been approved
> > for U.S. patents.
>
> > Is anyone knowledgable about the patent application willing to
> > transfer the patent application context to me and disclose why it
> > hasn't been approved as a U.S. patent.
>
> > My guess is it may never be approved by U.S. Patent Office to be a
> > patent, the reason is not its novelty violation, but its context
> > didn't disclose enough information about the 3-bit addition circuit, a
> > requirement for any patent application to be approved to be a U.S.
> > patent. At least those skilled in the art cannot get the idea what is
> > done within its circuit having an encircled '+' with 3 inputs and 2
> > outputs.
>
> > Altera another sister patent application "Arithmetic Structure is for
> > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate.
>
> > Thank you.
>
> > Weng
>
> I don't know why Altera wouldn't disclose info on the structure being
> used in a device. *It is relatively inexpensive to reverse engineer a
> chip, so if it is not disclosed in a patent, it is not protected and
> is vulnerable to being copied.
>
> What exactly *does* the patent claim? *Maybe the design inside the
> circled + is not really novel and only the design around the circle is
> novel enough to be patented?
>
> In general, I think a three in put adder is *very useful*. *I've never
> seen such a circuit, I guess the carry chain has multiple bits, eh?
>
> Rick- Hide quoted text -
>
> - Show quoted text -


Hi Rick,
Here is a link to Stratix IV Device Handbook Volumn 1 and page 43
shows the invention circuit:
http://www.altera.com/literature/hb/...v/stx4_5v1.pdf

Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it
describes two applications: multiplication and correlation function.

Any other applications? With multiplier hardware structure specially
introduced in FPGA, is multiplication circuit still used for
multiplication?

Weng

Weng Tianxiang

On Jun 15, 10:13 am, Weng Tianxiang <wtx...@gmail.com> wrote:
> On Jun 15, 4:36 am, rickman <gnu...@gmail.com> wrote:
>
>
>
> > On Jun 14, 1:21 pm, Weng Tianxiang <wtx...@gmail.com> wrote:
>
> > > Hi,
> > > I recently read Altera Stratix II, III and IV device handbook and
> > > found its 3-bit addition circuit is really a genius invention. But I
> > > was surprised to find that Altera patent application "Logic Cell
> > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has
> > > not been approved to be a patent so far today, even though many Altera
> > > later patent applications based on the invention have been approved
> > > for U.S. patents.
>
> > > Is anyone knowledgable about the patent application willing to
> > > transfer the patent application context to me and disclose why it
> > > hasn't been approved as a U.S. patent.
>
> > > My guess is it may never be approved by U.S. Patent Office to be a
> > > patent, the reason is not its novelty violation, but its context
> > > didn't disclose enough information about the 3-bit addition circuit, a
> > > requirement for any patent application to be approved to be a U.S.
> > > patent. At least those skilled in the art cannot get the idea what is
> > > done within its circuit having an encircled '+' with 3 inputs and 2
> > > outputs.
>
> > > Altera another sister patent application "Arithmetic Structure is for
> > > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate.
>
> > > Thank you.
>
> > > Weng
>
> > I don't know why Altera wouldn't disclose info on the structure being
> > used in a device. It is relatively inexpensive to reverse engineer a
> > chip, so if it is not disclosed in a patent, it is not protected and
> > is vulnerable to being copied.
>
> > What exactly *does* the patent claim? Maybe the design inside the
> > circled + is not really novel and only the design around the circle is
> > novel enough to be patented?
>
> > In general, I think a three in put adder is *very useful*. I've never
> > seen such a circuit, I guess the carry chain has multiple bits, eh?
>
> > Rick- Hide quoted text -
>
> > - Show quoted text -
>
> Hi Rick,
> Here is a link to Stratix IV Device Handbook Volumn 1 and page 43
> shows the invention circuit:http://www.altera.com/literature/hb/...v/stx4_5v1.pdf
>
> Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it
> describes two applications: multiplication and correlation function.
>
> Any other applications? With multiplier hardware structure specially
> introduced in FPGA, is multiplication circuit still used for
> multiplication?

Although they show the interconnections being used, they don't show
the logic implemented in the LUTs. The carry from one bit to the next
is done with two signals each of which has the same weight. As far as
I can tell, this is just a pair of cascaded adders, the first done in
the LUTs and the second done in dedicated hardware. The only novelty
is that instead of adding two inputs with one adder chain (the LUTs)
and then adding the result to the third input with the dedicated
hardware chain, they add all three input bits using the LUTs and feed
both carry bits into the dedicated hardware chain which means the
carry chain always uses the fast, dedicated hardware.

Does that sound like a patent worthy invention to you? I don't really
know what is and what is not worthy of a patent. But other patents
"based" on this patent will not be affected by the validity of this
patent. Even if this patent is upheld, ***I*** could patent some
additional feature that uses this design as a starting point. I just
can't build it without permission from the patent holder of the
original design. Still, this means he/she couldn't use my idea
without my permission either.

Rick

rickman

On Jun 15, 8:39*am, rickman <gnu...@gmail.com> wrote:
> On Jun 15, 10:13 am, Weng Tianxiang <wtx...@gmail.com> wrote:
>
>
>
>
>
> > On Jun 15, 4:36 am, rickman <gnu...@gmail.com> wrote:
>
> > > On Jun 14, 1:21 pm, Weng Tianxiang <wtx...@gmail.com> wrote:
>
> > > > Hi,
> > > > I recently read Altera Stratix II, III and IV device handbook and
> > > > found its 3-bit addition circuit is really a genius invention. But I
> > > > was surprised to find that Altera patent application "Logic Cell
> > > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has
> > > > not been approved to be a patent so far today, even though many Altera
> > > > later patent applications based on the invention have been approved
> > > > for U.S. patents.
>
> > > > Is anyone knowledgable about the patent application willing to
> > > > transfer the patent application context to me and disclose why it
> > > > hasn't been approved as a U.S. patent.
>
> > > > My guess is it may never be approved by U.S. Patent Office to be a
> > > > patent, the reason is not its novelty violation, but its context
> > > > didn't disclose enough information about the 3-bit addition circuit, a
> > > > requirement for any patent application to be approved to be a U.S.
> > > > patent. At least those skilled in the art cannot get the idea what is
> > > > done within its circuit having an encircled '+' with 3 inputs and 2
> > > > outputs.
>
> > > > Altera another sister patent application "Arithmetic Structure is for
> > > > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate..
>
> > > > Thank you.
>
> > > > Weng
>
> > > I don't know why Altera wouldn't disclose info on the structure being
> > > used in a device. *It is relatively inexpensive to reverse engineer a
> > > chip, so if it is not disclosed in a patent, it is not protected and
> > > is vulnerable to being copied.
>
> > > What exactly *does* the patent claim? *Maybe the design inside the
> > > circled + is not really novel and only the design around the circle is
> > > novel enough to be patented?
>
> > > In general, I think a three in put adder is *very useful*. *I've never
> > > seen such a circuit, I guess the carry chain has multiple bits, eh?
>
> > > Rick- Hide quoted text -
>
> > > - Show quoted text -
>
> > Hi Rick,
> > Here is a link to Stratix IV Device Handbook Volumn 1 and page 43
> > shows the invention circuit:http://www.altera.com/literature/hb/...v/stx4_5v1.pdf
>
> > Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it
> > describes two applications: multiplication and correlation function.
>
> > Any other applications? With multiplier hardware structure specially
> > introduced in FPGA, is multiplication circuit still used for
> > multiplication?
>
> Although they show the interconnections being used, they don't show
> the logic implemented in the LUTs. *The carry from one bit to the next
> is done with two signals each of which has the same weight. *As far as
> I can tell, this is just a pair of cascaded adders, the first done in
> the LUTs and the second done in dedicated hardware. *The only novelty
> is that instead of adding two inputs with one adder chain (the LUTs)
> and then adding the result to the third input with the dedicated
> hardware chain, they add all three input bits using the LUTs and feed
> both carry bits into the dedicated hardware chain which means the
> carry chain always uses the fast, dedicated hardware.
>
> Does that sound like a patent worthy invention to you? *I don't really
> know what is and what is not worthy of a patent. *But other patents
> "based" on this patent will not be affected by the validity of this
> patent. *Even if this patent is upheld, ***I*** could patent some
> additional feature that uses this design as a starting point. *I just
> can't build it without permission from the patent holder of the
> original design. *Still, this means he/she couldn't use my idea
> without my permission either.
>
> Rick- Hide quoted text -
>
> - Show quoted text -

Hi Rick,
There are two novel points there:
1. It transfers 3 adders into 2 adders which was described very clear:
nobody before had invented that point.
2. Circuit is marked by circled '+' with 3 inputs and 2 outputs whose
internal structure wasn't shown.
3. I am sure there may be more than 20 claims in the application as
Altera patent claim trandition goes.

Weng

Weng Tianxiang

You can try to go to USPTO database and lookup the history of this
patent application.
It's not under the patent search, but under "http://www.uspto.gov" ->
"Patents" -> "view in PAIR" -> "public PAIR".
This database contains a complete history of the patent, including the
correspondence with patent examiners, etc.
Also, can you post the patent application number.

- outputlogic

http://outputlogic.com

OutputLogic

On Jun 15, 9:23*am, OutputLogic <evgen...@gmail.com> wrote:
> You can try to go to USPTO database and lookup the history of this
> patent application.
> It's not under the patent search, but under "http://www.uspto.gov" ->
> "Patents" -> "view in PAIR" -> "public PAIR".
> This database contains a complete history of the patent, including the
> correspondence with patent examiners, etc.
> Also, can you post the patent application number.
>
> - outputlogic
>
> http://outputlogic.com

Hi,
Its application number is 10/718,968 filed on November 21, 2003.

Weng

Weng Tianxiang

On Jun 15, 9:23*am, OutputLogic <evgen...@gmail.com> wrote:
> You can try to go to USPTO database and lookup the history of this
> patent application.
> It's not under the patent search, but under "http://www.uspto.gov" ->
> "Patents" -> "view in PAIR" -> "public PAIR".
> This database contains a complete history of the patent, including the
> correspondence with patent examiners, etc.
> Also, can you post the patent application number.
>
> - outputlogic
>
> http://outputlogic.com

Hi OutputLogic,
Thank you for your information.

I had searched the website before I posed this message and got the
error information:
"Sorry, the entered Application Number "10/718968" is not available.
The number may have been incorrectly typed, or assigned to an
application
that is not yet available for public inspection."

I don't know why I got the error message.

10/718968 is available from reference literature in the invention:
"Programmable Logic Device Having Complex Logic Blocks with Improved
Logic Cell Functionality", patent number 7,394,287, by Alera from
following website:
http://www.google.com/patents/about?...=0&as_maxy_is=

Weng

Weng Tianxiang

On Jun 15, 8:39*am, rickman <gnu...@gmail.com> wrote:
> On Jun 15, 10:13 am, Weng Tianxiang <wtx...@gmail.com> wrote:
>
>
>
>
>
> > On Jun 15, 4:36 am, rickman <gnu...@gmail.com> wrote:
>
> > > On Jun 14, 1:21 pm, Weng Tianxiang <wtx...@gmail.com> wrote:
>
> > > > Hi,
> > > > I recently read Altera Stratix II, III and IV device handbook and
> > > > found its 3-bit addition circuit is really a genius invention. But I
> > > > was surprised to find that Altera patent application "Logic Cell
> > > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has
> > > > not been approved to be a patent so far today, even though many Altera
> > > > later patent applications based on the invention have been approved
> > > > for U.S. patents.
>
> > > > Is anyone knowledgable about the patent application willing to
> > > > transfer the patent application context to me and disclose why it
> > > > hasn't been approved as a U.S. patent.
>
> > > > My guess is it may never be approved by U.S. Patent Office to be a
> > > > patent, the reason is not its novelty violation, but its context
> > > > didn't disclose enough information about the 3-bit addition circuit, a
> > > > requirement for any patent application to be approved to be a U.S.
> > > > patent. At least those skilled in the art cannot get the idea what is
> > > > done within its circuit having an encircled '+' with 3 inputs and 2
> > > > outputs.
>
> > > > Altera another sister patent application "Arithmetic Structure is for
> > > > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate..
>
> > > > Thank you.
>
> > > > Weng
>
> > > I don't know why Altera wouldn't disclose info on the structure being
> > > used in a device. *It is relatively inexpensive to reverse engineer a
> > > chip, so if it is not disclosed in a patent, it is not protected and
> > > is vulnerable to being copied.
>
> > > What exactly *does* the patent claim? *Maybe the design inside the
> > > circled + is not really novel and only the design around the circle is
> > > novel enough to be patented?
>
> > > In general, I think a three in put adder is *very useful*. *I've never
> > > seen such a circuit, I guess the carry chain has multiple bits, eh?
>
> > > Rick- Hide quoted text -
>
> > > - Show quoted text -
>
> > Hi Rick,
> > Here is a link to Stratix IV Device Handbook Volumn 1 and page 43
> > shows the invention circuit:http://www.altera.com/literature/hb/...v/stx4_5v1.pdf
>
> > Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it
> > describes two applications: multiplication and correlation function.
>
> > Any other applications? With multiplier hardware structure specially
> > introduced in FPGA, is multiplication circuit still used for
> > multiplication?
>
> Although they show the interconnections being used, they don't show
> the logic implemented in the LUTs. *The carry from one bit to the next
> is done with two signals each of which has the same weight. *As far as
> I can tell, this is just a pair of cascaded adders, the first done in
> the LUTs and the second done in dedicated hardware. *The only novelty
> is that instead of adding two inputs with one adder chain (the LUTs)
> and then adding the result to the third input with the dedicated
> hardware chain, they add all three input bits using the LUTs and feed
> both carry bits into the dedicated hardware chain which means the
> carry chain always uses the fast, dedicated hardware.
>
> Does that sound like a patent worthy invention to you? *I don't really
> know what is and what is not worthy of a patent. *But other patents
> "based" on this patent will not be affected by the validity of this
> patent. *Even if this patent is upheld, ***I*** could patent some
> additional feature that uses this design as a starting point. *I just
> can't build it without permission from the patent holder of the
> original design. *Still, this means he/she couldn't use my idea
> without my permission either.
>
> Rick- Hide quoted text -
>
> - Show quoted text -

Hi Rick,
"The only novelty
is that instead of adding two inputs with one adder chain (the LUTs)
and then adding the result to the third input with the dedicated
hardware chain, they add all three input bits using the LUTs and feed
both carry bits into the dedicated hardware chain which means the
carry chain always uses the fast, dedicated hardware. "

The method I found was invented as early as 1963 by C.S. Wallace in
paper "A suggestion for a Fast Multiplier"
http://www.caip.rutgers.edu/~bushnel...llacepaper.pdf

The circuit circled in '+' with 3 inputs and 2 outputs is novelty in
my opinion, but they didn't disclose it.

Weng

Weng Tianxiang

On Jun 15, 5:06*pm, Muzaffer Kal <k...@dspia.com> wrote:
> On Mon, 15 Jun 2009 16:44:19 -0700 (PDT), Weng Tianxiang
>
> <wtx...@gmail.com> wrote:
> >The circuit circled in '+' with 3 inputs and 2 outputs is novelty in
> >my opinion, but they didn't disclose it.
>
> It would be interesting to see if it's anything other than a 3:2
> compressor.
> --
> Muzaffer Kal
>
> DSPIA INC.
> ASIC/FPGA Design Services
>
> http://www.dspia.com

Here is another good reference published in 1994 by Stanford Ph. D
student Gary W. Bewick as his dissatation paper.

ftp://reports.stanford.edu/pub/cstr/...-TR-94-617.pdf,
page 34 where a 3:2 compressor was shown graphically.

Weng

Weng Tianxiang