Signal assignment inside for loop

Hello all,
I'm new to VHDL and having a problem.

I know that signal assignment does not take effect until the end of the process unlike the variable assignment.
ie cnt <= cnt +1;
out <= cnt;
If cnt is a signal then out will have the value of cnt before adding 1.

My problem is I want to have same kind of signal assignment inside a for loop
ie for i 0 to 2 loop
cnt <= cnt +1;
end loop;

cnt is a signal, how can i do that and have the right cnt value?

Thanks.

krkrkr

[debayan_p]

for i 0 to 2 loop
cnt <= cnt +1;
end loop;

The above is ok if you declare 'cnt' as a variable. Is it necessary to declare it as a signal ?

Later when ur looping is complete you can saaign the variable 'cnt' to a signal or an output port.

debayan_p