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Signal assignment inside for loop

 
 
krkrkr krkrkr is offline
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Join Date: Jun 2009
Posts: 7
 
      06-14-2009
Hello all,
I'm new to VHDL and having a problem.

I know that signal assignment does not take effect until the end of the process unlike the variable assignment.
ie cnt <= cnt +1;
out <= cnt;
If cnt is a signal then out will have the value of cnt before adding 1.

My problem is I want to have same kind of signal assignment inside a for loop
ie for i 0 to 2 loop
cnt <= cnt +1;
end loop;

cnt is a signal, how can i do that and have the right cnt value?

Thanks.
 
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debayan_p debayan_p is offline
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Join Date: Jun 2009
Posts: 23
 
      06-17-2009
for i 0 to 2 loop
cnt <= cnt +1;
end loop;

The above is ok if you declare 'cnt' as a variable. Is it necessary to declare it as a signal ?

Later when ur looping is complete you can saaign the variable 'cnt' to a signal or an output port.
 
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