Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Signal assignment inside for loop

Thread Tools

Signal assignment inside for loop

krkrkr krkrkr is offline
Junior Member
Join Date: Jun 2009
Posts: 7
Hello all,
I'm new to VHDL and having a problem.

I know that signal assignment does not take effect until the end of the process unlike the variable assignment.
ie cnt <= cnt +1;
out <= cnt;
If cnt is a signal then out will have the value of cnt before adding 1.

My problem is I want to have same kind of signal assignment inside a for loop
ie for i 0 to 2 loop
cnt <= cnt +1;
end loop;

cnt is a signal, how can i do that and have the right cnt value?

Reply With Quote
debayan_p debayan_p is offline
Junior Member
Join Date: Jun 2009
Posts: 23
for i 0 to 2 loop
cnt <= cnt +1;
end loop;

The above is ok if you declare 'cnt' as a variable. Is it necessary to declare it as a signal ?

Later when ur looping is complete you can saaign the variable 'cnt' to a signal or an output port.
Reply With Quote

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off

Similar Threads
Thread Thread Starter Forum Replies Last Post
Triple nested loop python (While loop insde of for loop inside ofwhile loop) Isaac Won Python 9 03-04-2013 10:08 AM
Assignment to output signal from internal signal not istantaneous dibacco73 VHDL 1 02-12-2009 11:28 PM
Re: How to loop through a list while inside the loop, the list size may be decreased? Roedy Green Java 3 09-13-2008 01:51 AM
"Target of signal assignment is not a signal" Nicolas Moreau VHDL 9 07-25-2007 04:21 PM
Loop Inside loop for writing text lines Aggelos ASP General 2 11-12-2003 09:59 AM