vhdl loopback

Hey all, for a computer organisation and design project we have to write a 4 bit alu in vhdl... so far so good, except i can not for the life of me get my program counter to increment. The program counter is a component with the current PC as input, and it outputs the new PC (it may be plus 1, or it may be plus an offset address for a branch operation)..

This is working ok, i enter a value of 0 and get out a value of 1, and this value is set to a signal in the main CPU component... how can i pass this signal back into the input? im pretty sure ive tried everything - i set both the input and the output as buffer but whenever i seem to think its wired up correctly, the output just doesnt change and so it doesnt get back into the input and the PC never increments, which leads to a useless cpu haha

Program counter code:

entity PCounter is
    Port ( pc : buffer STD_LOGIC_VECTOR (5 downto 0);
           branchAddr : in  STD_LOGIC_VECTOR (5 downto 0);
           incrementorbranch : in  STD_LOGIC;
			  ALUControl: in std_logic_vector(2 downto 0);
           outputPC : buffer  STD_LOGIC_VECTOR (5 downto 0));
end PCounter;

architecture Behavioral of PCounter is
component ALU16 is
	port(opcodeIn	: in std_logic_vector (2 downto 0);
		  aIn	: in std_logic_vector (5 downto 0);
		  bIn	: in std_logic_vector (5 downto 0);
		  output : out std_logic_vector (5 downto 0);
		  overflow	: out std_logic;
		  over2C		: out std_logic;
		  zero		: out std_logic);
end component;
signal pcPlusOne:std_logic_vector(5 downto 0);
signal AluBit:std_logic_vector(6 downto 0);
signal pcPlusAddress:std_logic_vector(5 downto 0);
begin
	IncrementPCAlu : ALU16 port map("000","000001",pc,pcPlusOne,AluBit(0),AluBit(1),AluBit(2));
	AddrALU : ALU16 port map(ALUControl,pcPlusOne,branchAddr,pcPlusAddress,AluBit(3),AluBit(4),AluBit(5));
	process(pcPlusOne,pcPlusAddress,incrementorbranch,pc)
	begin
		case incrementorbranch is
			when '0' => outputPC <= pcPlusOne;
			when '1' => outputPC <= pcPlusAddress;
			when others => outputPC <= pcPlusOne;
		end case;
	end process;
end Behavioral;	

Main CPU Code (watered down to show only the program counter stuff)

entity CPU is
	Port ( Clk : in  STD_LOGIC;
           ExecuteControl : in  STD_LOGIC;
			  ProgramData : in std_logic_vector(15 downto 0));
end CPU;
architecture Behavioral of CPU is
component PCounter is
    Port ( pc : buffer  STD_LOGIC_VECTOR (5 downto 0);
           branchAddr : in  STD_LOGIC_VECTOR (5 downto 0);
           incrementorbranch : in  STD_LOGIC;
			  ALUControl: in std_logic_vector(2 downto 0);
           outputPC : out  STD_LOGIC_VECTOR (5 downto 0));
end component;
signal PC : std_logic_vector(5 downto 0);
signal alteredPC: std_logic_vector(5 downto 0);
signal newPC:std_logic_vector(5 downto 0);

begin
	progCount: PCounter port map(newPC,sExtendOut,zeroANDBranch,ALUctrlOut,alteredPC);
end Behavioral;

yeh so basically i need newPC to equal alteredPC - but i cant get it to work and i have no more ideas....

any help would be so appreciated!!! thanks

GracelessROB

[joris]

newPC <= alteredPC

but then you have to have a clock in there, to have the effect of the assignment only appear on the next clock cycle :-/

joris

[GracelessROB]

hmnn ive already tried that, i put it in a process with alteredPC as the sensitivity list, and newpc never changes...

GracelessROB