CRC8 post-routing problems

Hi,

I have a VHDL code for a CRC8 structure. It clocks in the data, computes the CRC, and then outputs a signal which indicated whether the CRC register is all 0 or not. The pre-synthesis simulations are fine, and so are the post-synthesis simulations. However, when I run the post-routing simulations, I get some errors that I am not sure where comes from. I sometimes, in the middle of the process, get a wrong value in the crc_r register (for some reason, I do not have access to the crc_i and crc_c registers when doing the post-routing simulation). Below is my code, and I was wondering if someone has an input to perhaps why this is failing after placing and routing. And maybe if there are more robust ways of doing the CRC8 algorithm when the purpose is to implement it on an FPGA.

Thanks!

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY crc8 IS
PORT(
L : IN std_logic;
E : IN std_logic;
w : IN std_logic;
CLK : IN std_logic;
Q : OUT std_logic
);

END entity crc8 ;

ARCHITECTURE struct OF crc8 IS
signal crc_c, crc_r, crc_i : std_logic_vector(7 downto 0);
BEGIN

crc_i <= crc_r;

crc_c(0) <= w xor crc_i(7);
crc_c(1) <= crc_i(0);
crc_c(2) <= crc_i(1);
crc_c(3) <= crc_i(2);
crc_c(4) <= crc_i(3) xor crc_i(7);
crc_c(5) <= crc_i(4) xor crc_i(7);
crc_c(6) <= crc_i(5);
crc_c(7) <= crc_i(6);

process(CLK,L,E)
begin
if E = '1' then
if L = '1' then
crc_r <= "00000000";
elsif falling_edge(CLK) then
crc_r <= crc_c;
end if;
end if;
end process;

process(CLK,crc_r)
begin
if falling_edge(CLK) then
if crc_r = "00000000" then
Q <= '0';
else
Q <= '1';
end if;
end if;
end process;

END ARCHITECTURE struct;

c64