Clock task from Verilog to VHDL

Hello, how can I declare from verilog -->> to VHDL
initial
clk = 1'b0;
always
clk = #10 ~clk;


And these
`define RESET_TIME 8

initial
reset = 1'b1;
task reset;
begin
reset <= #1 1'b1;
tk_wait(`RESET_TIME);
reset <= #1 1'b0;

task tk_wait;
input[31] count;
integer i;
begin
for(i=0;i<=count;i=i+1)
@(posedge clk);
end
endtask


Anybody, please help me in solution these a little problem, cause I`m new in VHDL. THANKS

Karper1986