Negative/positive slack and clock frequency

Hi,

I'm working on a design which is synthesized by SiliconBlue's iCEcube software (which again uses Magma for the actual synthesis). I've come across a little peculiarity (at least for me, since I'm quite new to the VHDL programming for FPGAs). The main input clock is running at a frequency of 16MHz, but after looking at the static timing report, there are some paths that cause negative slack. However, if I use a 32MHz clock as input, and then use a clock divider to produce a 16MHz clock (which I then use as the main clock), everything is fine, that is, I only have positive slack. So I figured, if I can somehow "emulate" a clock division (by 2) without actually dividing the clock (I guess to make some additional delay which seems to work out nicely for my design), then I can use a 16MHz clock at the input. Is there a way of doing this? Also, since I'm new to this, are there other things I should do instead with my design? (in general terms, of course, since it would be too much code to post anything on this forum). Would a dummy structure to cause some needed delay be a bad design approach?

Thanks in advance!

c64