Problem using Unsigned in Modelsim

Hey guys,

I'm currently learning to code in VHDL and are having a problem implementing unsigned vectors. I'm using ISE 9.2i and ModelSim PE 6.5a. I wrote the code using Standard Logic Vector and it executes no problem, but when I try implement it using unsigned vectors I get an error (among others) that "Identifier "unsigned" is not directly visible."

Unfortunately the task does not allow modification of the entity declaration, so I have to use the unsigned vector. Here's code as it stands:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity CountQ1 is
port(clk,Ld8,Enable: in STD_LOGIC;
Q: out UNSIGNED(3 downto 0));
end CountQ1;

architecture Behavioral of CountQ1 is
signal Count: UNSIGNED(3 downto 0);
begin
process(clk)
begin
if (clk='1' and clk'event) then
if (Ld8 = '1' or Count = "0011") then
Count <= "1000";
elsif Enable = '1' then
end if;
Count <= Count-"0001";
end if;
end if;
end process;
Q <= Count;
end Behavioral;



the library declaration given includes only STD_LOGIC_1164 and NUMERIC_BIT, but I didn't see how the latter was relevant since I dont use numeric_bit vectors and so removed it and replaced with NUMERIC_STD.

Any hints or tips would be greatly appreciated
Cheers

ElecB