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Avoiding gated clocks for counters

 
 
c64 c64 is offline
Junior Member
Join Date: Apr 2009
Posts: 11
 
      05-05-2009
Hi,

After reading some posts on this newsgroup, I have understood that gated clocks is something one would like to avoid in FPGA design. The following code is for a counter:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY counter2rev2 IS
PORT(
ENC : IN std_logic;
CLK2 : IN std_logic;
COUNT2 : OUT std_logic_vector (18 DOWNTO 0)
);


END counter2rev2 ;

ARCHITECTURE struct OF counter2rev2 IS
signal count2Int : std_logic_vector(18 downto 0);
constant allOnes : std_logic_vector(18 downto 0) := (others => '1');
BEGIN
counter : process (ENC,CLK2)
begin
if ENC = '0' then
count2Int <= (others => '0');
elsif rising_edge(CLK2) then
if (unsigned(count2Int) = unsigned(allOnes)) then
count2Int <= (others => '0');
else
count2Int <= (unsigned(count2Int) + '1');
end if;
end if;
end process;
COUNT2 <= count2Int;
END ARCHITECTURE struct;


If I compile this as a stand-alone code, I get no warnings or errors. However, if I use it as a component in a larger system, I get the warning message that "The clock for counter 'count2Int' is gated", highlighting the line "count2Int <= (unsigned(count2Int) + '1');"

How should I change the design to avoid this gated clock warning?

Thanks!
 
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jeppe jeppe is offline
Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 348
 
      05-06-2009
Well the problem can't be found in this code.
you must look at the path of CLk2, which properly scale down.

Jeppe
 
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