Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Intro VHDL - Questions

Thread Tools

Intro VHDL - Questions

nihilanth100 nihilanth100 is offline
Junior Member
Join Date: Apr 2009
Posts: 1
Hey all, I just discovered these forums today and saw how many people have been helped with questions. My class just jumped into VHDL recently and i've been struggling with the first assignment and with two more on the way I really need to learn this stuff.

I checked out The Student's Guide to VHDL recently and its helping a bit.

The first assignment involves building the vhdl model of 74LVQ163

Its a 4-bit presettable counter. Were supposed to be just getting the hang of VHDL by implementing this based off of a basic counter which he gave the code for, as well as writing a test bench. Theres a truth table in the pdf file to code the processes off of but im not sure where to start.

library IEEE;
use IEEE.STD_LOGIC_1164.all;  

entity basic_cnt is
		 clock, sel, a, b : in STD_LOGIC;
		 reset : in STD_LOGIC;
		 Qout : out STD_LOGIC_VECTOR(3 downto 0);
		 q: out std_logic
end basic_cnt;

architecture basic_cnt_arch of basic_cnt is
signal Qint: STD_LOGIC_VECTOR (3 downto 0);	
	signal s: std_logic;

	process (clock, reset)
	   if reset ='1' then  
	      Qint <= "0000"; 
	      if clock'event and clock = '1' then
	        if Qint<"1001" then
	          Qint<=Qint + '1';
	        end if;
	     end if;
	   end if;
	end process;
	Qout <= Qint; 
process (sel, a, b)

	s <=  sel;
	case s is	
		when '0' => 		q <= a;	
		when '1' => 		q <= b;
		when others =>		q <= 'X';
	end case;
end process;

end basic_cnt_arch;
Im trying to dissect this code to rebuild it as a 4 bit counter and slightly understand how to set the code to read the clear to reset the counter but not enough to build the code for the counting, nor do I understand the cases in the process at the bottom. The assignment is already due, and hes posting the next one today so I wanted to fully understand what we had to do before moving on. All im looking for is help on how I should be going about understanding this and how im supposed to be coding it as well as any other resources (like tutorials) on how to write this language. Thanks in advance for any help. This seems pretty easy, im slightly embarrassed that I'm so lost
Reply With Quote

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off

Similar Threads
Thread Thread Starter Forum Replies Last Post
VHDL-2002 vs VHDL-93 vs VHDL-87? afd VHDL 1 03-23-2007 09:33 AM
First post - intro - Questions about the nature of MCSE/Study c_berry MCSE 4 09-13-2006 05:35 AM
Python Magazine exists! (was: Python intro questions) Mark Python 21 06-30-2004 04:33 AM
Re: Python Magazine exists! (was: Python intro questions) Mark Python 2 06-27-2004 10:16 PM
Re: OT:Intro to my new baby!!! Consultant MCSE 0 08-18-2003 03:00 PM