constants as of array of integers, for loops

I have been searching around for more than a day intensively but I was unable to find any answer. I am having a problem with constants substitution in VHDL and I have no idea why.

I have a package where I defined a constant as an array of integers with the index from ( 0 downto 0). The constant I am talking about is g_nr_of_ahb_masters and is the last one in the post below.

package utel_crc_ccu_config_pkg is
   constant g_nr_of_base_clks         : integer := 1;
   subtype ccu_base_clk_cfg_cell_type is array_of_integer_type(g_nr_of_base_clks-1 downto 0);
   type ccu_base_clk_cfg_array_type   is array (integer range <>) of ccu_base_clk_cfg_cell_type;
   constant g_base_clk_cfg_array      : ccu_base_clk_cfg_array_type (0 to 2) :=  ( (0 => 3) ,  (0 => 0) ,  (0 => 0) );
...
constant g_nr_of_ahb_masters       : ccu_base_clk_cfg_cell_type := g_base_clk_cfg_array(2);

As can be seen g_nr_of_ahb_masters(0) is equal with 0

The tricky part is that I am using this constant in a process statement where for loops are defined as shown below

 mux_proc : process (ahb_master_auto_int, branch_clk_int, hclken_int, gated_clk_override_int)
   begin   
      for i in 0 to g_nr_of_base_clks-1 loop
         if (g_nr_of_ahb_masters(i) > 0) then
	    -- it goes here WHY??????   since  g_nr_of_ahb_masters(0) is 0, isn't it
	 end if;
      end loop;
   end process mux_proc;

When parsing this code it tries to go inside the "if" statement but it should avoid it.

If I replace g_nr_of_ahb_masters(i) with g_nr_of_ahb_masters(0) it does not go inside the "if" anymore.

What am I doing wrong?
Thank you in advance for any answers,
Octavian

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