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[mbrook10]

I'm building a simple processor that does pipe lining. I wanted to know if there is anyway I can call a component I made in another file within a case statement. Here's some of my code.

architecture behv of MEM is

COMPONENT CPU_Memory
port(
inData : in std_logic_vector(31 downto 0);
address : in std_logic_vector(31 downto 0);
read : in std_logic;
write : in std_logic;
clk : in std_logic;
enable : in std_logic;
outData : out std_logic_vector(31 downto 0)
);
end COMPONENT;
signal BLANK: std_logic_vector(31 downto 0);
begin

BLANK <= std_logic_vector(to_unsigned(0, 31));
process
begin
case opcode is
when "010000" => --LW
-- access "address" and output "outData"
MEMLW: Memory
portmap(BLANK,in_address,'1','0',clk,'1',outRead);


When I call port map within my case statement I get an error saying illegal sequential statement. I wanted to know if there was another way around it.