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VITAL needed for memories modeling ?

 
 
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      04-16-2009
Hi all

I am learning now modeling of memories of all kinds , RAM , SRAM , DRAM etc
...
My question is : Do I have to use VITAL in the memories models which are
behavioral , not for synthesis , or it is ok to use
the standard VHDL TIME generics to describe the true timing of a memory
modeled with VHDL ?

Thanks
EC


 
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