State machine incrementing

I have the following code in my state machine for an I2C controller.
Basically when I get to state data_out4, I want to increment the
variable "datacount" by 1. However I stay in that state for many clock
cycles and it increments many times. How can I code it so that it
increments the variable only once when I'm in that state? Thanks

elsif state = data_out1 then
sda_sig <= 'Z';
scl_sig <= '0';
elsif state = data_out2 then
if data_out(7-datacount) = '0' then
sda_sig <= '0';
else
sda_sig <= 'Z';
end if;
scl_sig <= '0';
elsif state = data_out3 then
if data_out(7-datacount) = '0' then
sda_sig <= '0';
else
sda_sig <= 'Z';
end if;
scl_sig <= '1';
elsif state = data_out4 then
if data_out(7-datacount) = '0' then
sda_sig <= '0';
else
sda_sig <= 'Z';
end if;
scl_sig <= '0';
datacount:=datacount+1;

zooplibob@gmail.com

Its interesting that it simulates correctly in the Xilinx simulator,
but when running on the CPLD, it increments as fast as possible.
I think this is more of a synthesis problem, because I could just
expand those lines instead of using the variable "datacount" hardcode
it from 0 to 7 and just copy and paste the whole thing 7 times, but it
seems like I should be able to write it like this and have it
synthesize properly

Jeff

<> wrote in message
news:cfda7a27-6949-48a8-9fad-...
>I have the following code in my state machine for an I2C controller.
> Basically when I get to state data_out4, I want to increment the
> variable "datacount" by 1. However I stay in that state for many clock
> cycles and it increments many times. How can I code it so that it
> increments the variable only once when I'm in that state? Thanks
>

1. Use a synchronous process
process(Clock)
begin
if rising_edge(Clock) then
... -- Put your code here
end if;
end process;

2. Synchronize all inputs the the clock before using
3. Simulate
4. Perform static timing analysis

Kevin Jennings

KJ

[Ukanbal]

Kevin,

I don't think synchronizing it with a clock will work. His problem is that he stays inside the 4th state for more then 1 clock cycle and as long as he is in there he doesn't want more than 1 increment to occur.

I am not sure if my solution is going to work or not but give this a try.
First create a 1 bit signal and set it to '1' in all the other states and when it comes to state 4 before the increment check that signal with an if statement. This way unless it goes into another state the newsignal that u set will stay as 0 and there wont be any increments


elsif state = data_out1 then
sda_sig <= 'Z';
scl_sig <= '0';
NEWSIGNAL <= '1';
elsif state = data_out2 then
if data_out(7-datacount) = '0' then
sda_sig <= '0';
else
sda_sig <= 'Z';
end if;
scl_sig <= '0';
NEWSIGNAL <= '1'
elsif state = data_out3 then
if data_out(7-datacount) = '0' then
sda_sig <= '0';
else
sda_sig <= 'Z';
end if;
scl_sig <= '1';
NEWSIGNAL <= '1'
elsif state = data_out4 then
if data_out(7-datacount) = '0' then
sda_sig <= '0';
else
sda_sig <= 'Z';
end if;
scl_sig <= '0';

if NEWSIGNAL = '1' THEN
datacount:=datacount+1;
NEWSIGNAL <= '0';

I hope this helps,

Ugur KANBAL

Ukanbal