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VHDL - variable cnt1 : std_logic_vector(20 downto 0):= (cnt1'right => '1', others => '0');

 
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Old 03-12-2009, 06:13 PM   #1
Default variable cnt1 : std_logic_vector(20 downto 0):= (cnt1'right => '1', others => '0');


Hi,

I want to initialise a variable this way :
Code:
variable cnt1 : std_logic_vector(20 downto 0):= (cnt1'right => '1', others => '0');

I know i doesn't work, i want to know the correct way of doing this kind of initialisations.

Best regards,
Hassen.


hassenman
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Old 03-13-2009, 08:05 AM   #2
jeppe
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Try this

variable cnt1 : std_logic_vector(20 downto 0):= ((0)=>'1',others=>'0');

Your welcome
Jeppe


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Old 03-13-2009, 10:11 AM   #3
hassenman
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Hi,
Thank you, it worked !

Now i want to do the following :
Code:
if count = ((20 downto 11) => (others => '0'), (10 downto 0) => (others => '1')) then led <= '1'; end if;
or :
Code:
if count = ((20 downto 11) => (others => '0'), others => '1') then led <= '1'; end if;

Best regardes,
Hassen.


hassenman

Last edited by hassenman : 03-13-2009 at 10:17 AM.
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Old 03-14-2009, 09:08 AM   #4
jeppe
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The best way will be this:

if count="000000000011111111111" then
led<='1';
end if;

Your welcome
Jeppe


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