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VHDL - variable cnt1 : std_logic_vector(20 downto 0):= (cnt1'right => '1', others => '0'); |
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#1 |
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Hi,
I want to initialise a variable this way : Code:
I know i doesn't work, i want to know the correct way of doing this kind of initialisations. Best regards, Hassen. hassenman |
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#2 |
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Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 245
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Try this
variable cnt1 : std_logic_vector(20 downto 0):= ((0)=>'1',others=>'0'); Your welcome Jeppe jeppe |
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#3 |
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Junior Member
Join Date: Mar 2009
Posts: 3
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Hi,
Thank you, it worked ! Now i want to do the following : Code:
Code:
Best regardes, Hassen. hassenman Last edited by hassenman : 03-13-2009 at 10:17 AM. |
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#4 |
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Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 245
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The best way will be this:
if count="000000000011111111111" then led<='1'; end if; Your welcome Jeppe jeppe |
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