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VHDL - Please help with Post-PAR simulation |
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Hi,
I am using the Xilinx ISE 9.2i to generate the post-PAR simulation model and using ModelSim PE 6.1e to simulate. However, I get the warning below when I tried to perform post PAR simulation. And all the outputs have the 'U' values. Loading work.tb_post_par_sim(func) # ** Warning: (vsim-3473) Component instance "pnr_sim_inst : ssdn_bb_fpga_ert_timesim" is not bound. # Time: 0 ps Iteration: 0 Region: /tb_post_par_sim File: tb_post_par_sim.vhd Please help on resolving this. I already spent more than a week to deal with this problem. Thank you very much in advance. Mike Mike |
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