how to break out of for loop

hey guys, i am new to vhdl and was working on my projects, i wanted to use a for loop instead of a while loop and try to break out of the loop in case of a particular condition, can anyone let me know how to do it please?

and my friend told me that using a while loop may cause problems while synthesizing, can anyone explain why such a thing happens?

thanks

bharathbhushan.kn

[jeppe]

Im not sure but if my memory serves me well would could it be done with

FOR i IN 0 to 10 LOOP
....
IF i=5 THEN
EXIT
END IF;
....
END LOOP;

Check this as well: http://www.vdlande.com/VHDL/exits.html

Your welcome

jeppe