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VHDL - high impedance in VHDL

 
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Old 03-11-2009, 03:43 PM   #1
Default high impedance in VHDL


I usually use the std_logic type instead of bit, but I use it as "bits" anyway (as VHDL lacks support for don't care, and other values are mostly helpful for debugging)

There's one strange possible value, 'Z', described as high impedance. I kinda understand what it's supposed to do but I have no clue how one could use it in VHDL as-is. Could anyone show some examples of meaningful uses?


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Old 03-11-2009, 09:06 PM   #2
jeppe
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Well - 3-state buffers normally used whenever you want's to drive a line (a BUS) with more the one driver (output).

I got this example with a SPI Master and Slave (should be slaves to make more sence) - If you got two or more independent slave then only one of them allowed to drive the MISO line, hence must it be controlled with a statement like this:

MISO <= Shreg(7) when SS='0' else 'Z';

the complete code can be seen here:http://www.jjmk.dk/MMMI/Exercises/05...Ver2/index.htm

Hope it helped you
Jeppe


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