VHDL - I can use std_logic_vector only as input signal in Xilinx?

03-09-2009, 08:30 PM

Hi all,

When I assign an input signal as integer or real, I can only change
its value as a bit in test bench using Xilinx ISE 9.2i. Is
std_logic_vector the only right type for an input signal to input an
integer?

Thanks and bow.

Will

joris · 03-10-2009, 04:18 PM

A entity "should" have std_logic/std_logic_vector input/outputs only (this is required byt Xilinx ISE anyway)

You can use integer-type or other types in the test bench, as long as you convert them to/from std_logic_vector for inputs/outputs of the component that's being tested.

joris

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03-09-2009, 08:30 PM	#1
	I can use std_logic_vector only as input signal in Xilinx? Hi all, When I assign an input signal as integer or real, I can only change its value as a bit in test bench using Xilinx ISE 9.2i. Is std_logic_vector the only right type for an input signal to input an integer? Thanks and bow. Will

03-10-2009, 04:18 PM	#2
joris Member Join Date: Jan 2009 Posts: 31	A entity "should" have std_logic/std_logic_vector input/outputs only (this is required byt Xilinx ISE anyway) You can use integer-type or other types in the test bench, as long as you convert them to/from std_logic_vector for inputs/outputs of the component that's being tested. joris