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How could I output a real signal to std_logic_vector?

 
 
Will
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      03-09-2009
Hi all,

I'm really new to VHDL. I need to output a real signal. How could I
convert it to std_logic_vector? Or, could I output a real number
directly?
BTW, is there any way that I could monitor variables during test bench
simulation like debugging in other language?

Thanks and bow.
 
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JohnDuq JohnDuq is offline
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Posts: 88
 
      03-18-2009
Well, first you need some definition for your 'real' signal. If you can define it as a std_logic_vector then you are done.

signal clk_scaler : unsigned(20 downto 0);

What is your definition of 'real'? Not 'imaginary' (1 + i1)?

Yes, your test bench will let you see about anything that makes it through the compiler.
 
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Ukanbal Ukanbal is offline
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Join Date: Mar 2009
Posts: 9
 
      03-20-2009
in VHDL you can set your signal into any number. you can write any signed or unsigned number on it and your output signal will carry that value until you change it.

the question regarding creating a real signal... if you are talking about actual signals such as sinusoid i do not think you can do that. you can create a squarewave which is a simple clock in VHDL but thats about it.
 
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JohnDuq JohnDuq is offline
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      03-20-2009
You can create a sinusoid by using a look up table.
 
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