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VHDL - Uart

 
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Old 03-08-2009, 04:24 AM   #1
Default Uart


Hi. i have one design that is UART written in verilog code. The simulation is successfully done. However, when i program my design to the DE2 board and connect it to the PC using the RS232, there is no output shown in hyper terminal. i would like to ask a favor that help me to have a look on my coding to check that whether my design got any problem. Your effort would be much appreciated.


jasonkee111
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