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VHDL - problem with synthesizing for loop |
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#1 |
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this is my first post in this forum
i'm doing my graduation project simulation and implementaion for LTE physical layer but i faced many problems with synthesizing for loops i was to write a code for a block called interleaver used in a turbo coder the function of the inteleaver is to read a certain data vector (124 bits) and fill a matrix (47*4) ROW by ROW then read them column by column i filled the matrix without problems but when i tried to read the matrix column by column and store them in a 124 output data vector i made a nested loop of 2 for loops with bounds i checked the syntax every thing is ok but when synthesizing it (RTL schematic) i got error synthesizing now if this loop is not synthesizable i will have to write expression for each element (188 and when is the foor loop synthesizble and when not thanks in advance amr elhosiny |
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#2 |
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Member
Join Date: Jan 2009
Posts: 31
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A loop is synthesizable only if it's range won't change during run time;
This should be synthesizable: Code:
joris |
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#3 |
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Member
Join Date: Jan 2009
Posts: 31
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Just wanted to add, if the number is not static but there is a sane upper-bound, you might do such for loop with upper-bound and run time checking (that'll be functionally equivalent to doing all that manually anyway)
A loop with run-time bounds could also be described by using a state-machine construct but it'll take more clocks (but it can be useful to avoid too much logic being generated) - it is a bit more work but not that hard probably. joris |
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