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VHDL - problem with synthesizing for loop

 
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Old 03-05-2009, 12:17 PM   #1
Default problem with synthesizing for loop


this is my first post in this forum
i'm doing my graduation project
simulation and implementaion for LTE physical layer

but i faced many problems with synthesizing for loops

i was to write a code for a block called interleaver used in a turbo coder

the function of the inteleaver is to read a certain data vector (124 bits) and fill a matrix (47*4) ROW by ROW
then read them column by column

i filled the matrix without problems
but when i tried to read the matrix column by column and store them in a 124 output data vector i made a nested loop of 2 for loops with bounds
i checked the syntax every thing is ok but when synthesizing it (RTL schematic) i got error synthesizing

now if this loop is not synthesizable i will have to write expression for each element (188 )



and when is the foor loop synthesizble and when not


thanks in advance


amr elhosiny
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Old 03-06-2009, 12:30 PM   #2
joris
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A loop is synthesizable only if it's range won't change during run time;

This should be synthesizable:

Code:
constant N : integer := 1; -- any value v := (v'range => '0'); for i in 0 to N loop for j in i to min(i + 5,x'high - 1) loop -- loop body depending on i or j end loop; end loop;
This may mean a lot of logic is generated, depending on the loop body - To synthesise, the loop/loops will probably be unrolled completely.


joris
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Old 03-06-2009, 04:03 PM   #3
joris
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Just wanted to add, if the number is not static but there is a sane upper-bound, you might do such for loop with upper-bound and run time checking (that'll be functionally equivalent to doing all that manually anyway)

A loop with run-time bounds could also be described by using a state-machine construct but it'll take more clocks (but it can be useful to avoid too much logic being generated) - it is a bit more work but not that hard probably.


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