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VHDL - Pipelined signed multipliers

 
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Old 03-03-2009, 12:45 PM   #1
Default Pipelined signed multipliers


Hello,

I am trying to design a signed multiplier and I want to make it pipelined so I can improve its performance. I am experimenting with a Baugh-wooley multiplier but I am not quite sure how to go about this.

How is it possible to specify the number of pipelining stages in the multiplier or do I have to add registers at every input and output?

Any suggestions for this or other signed high performance multipliers is appreciated.

Thanks
Kaf


khodorf
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